Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action responds to the Amendment filed on 8/07/2026. Applicant's arguments filed with respect to the claims have been fully considered but they are not persuasive. The rejection(s) of the claims is maintained under prior art cited below. Applicant’s remarks are addressed in the Response to Applicant’s remarks section cited below.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-2 and 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukharev et al. (U.S. Pub. No. 2017/0286588 A1) in view of Oliva et al. (U.S. Pat. 8,650,527 B2).
As per claim 1, Sukharev discloses:
A method comprising:
identifying one or more locations of a time-dependent dielectric breakdown (TDDB) failure mechanism in an integrated circuit (IC) cell (See Para [0003]-[0008], i.e. A robust full-chip assessment technique for low-k TDDB is needed for evaluating the amount of the inter-metal dielectric degradation measured by the leakage current density and the mean time to failure during the circuit design, See Para [0009], i.e. techniques of full-chip assessment of time-dependent dielectric breakdown, See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics), wherein each location of the one or more locations comprises first and second conductor features separated by a dielectric region (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD);
identifying first and second nets comprising the respective first and second conductor features (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD);
for each location of the one or more locations, calculating a corresponding failure-in-time (FIT) value of a corresponding one or more FIT values based on respective first and second voltage signals of the first and second nets (See Para [0070]-[0086], i.e. the time-to-failure determination unit 970 determines time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns –[prior art base on model of electric path between metal lines, considered as the first and second voltage signals as cited above]).
Sukharev does not teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculating a total FIT rate based on the one or more FIT rates; and based on the total FIT rate, either modifying the IC cell or storing the IC cell in a storage device.
However, Oliva teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculating a total FIT rate based on the one or more FIT rates; and based on the total FIT rate, either modifying the IC cell or storing the IC cell in a storage device (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Oliva into the
teaching of Sukharev because it would allow for designer to determine an accurate
measure of how a circuit affects the reliability of a product in which the circuit is used
(See Col 1; Line 46-57).
As per claim 2, Sukharev and Oliva discloses all of the features of claim 1 as discloses above wherein Sukharev also discloses wherein the calculating each FIT rate of the one or more FIT rates comprises obtaining each of the corresponding first and second voltage signals from a simulation of a circuit comprising the first and second nets (See Para [0056]-[0059], i.e. Metal line structure shown in FIG. 5 is used as an example for simulating the electric path generation).
As per claim 10, Sukharev and Oliva discloses all of the features of claim 1 as discloses above wherein Oliva also discloses identifying failure information corresponding to a location of the one or more locations at which a FIT rate of the one or more FIT rates exceeds a threshold level, wherein the modifying the IC cell is based on the failure location (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
As per claim 11, Sukharev discloses:
A method comprising: for each cell of a plurality of cells in an integrated circuit (IC) layout diagram and each time-dependent dielectric breakdown (TDDB) failure mechanism of a plurality of TDDB failure mechanisms (See Para [0003]-[0008], i.e. A robust full-chip assessment technique for low-k TDDB is needed for evaluating the amount of the inter-metal dielectric degradation measured by the leakage current density and the mean time to failure during the circuit design, See Para [0009], i.e. techniques of full-chip assessment of time-dependent dielectric breakdown, See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics):
identifying one or more locations of the TDDB failure mechanism in the cell, wherein each location of the one or more locations comprises first and second conductor features separated by a dielectric region (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD);
identifying first and second nets comprising the respective first and second conductor features (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD); and
for each location of the one or more locations, calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates based on respective first and second voltage signals of the first and second nets (See Para [0070]-[0086], i.e. the time-to-failure determination unit 970 determines time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns –[prior art base on model of electric path between metal lines, considered as the first and second voltage signals as cited above]).
Sukharev does not teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculating a total FIT rate of the IC layout diagram based on the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells; and based on the total FIT rate, either modifying the IC layout diagram or storing the IC layout diagram in a storage device.
However, Oliva teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculating a total FIT rate of the IC layout diagram based on the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells; and based on the total FIT rate, either modifying the IC layout diagram or storing the IC layout diagram in a storage device (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Oliva into the
teaching of Sukharev because it would allow for designer to determine an accurate
measure of how a circuit affects the reliability of a product in which the circuit is used
(See Col 1; Line 46-57).
As per claim 12, Sukharev and Oliva discloses all of the features of claim 11 as discloses above wherein Sukharev also discloses wherein the calculating each FIT rate of the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells comprises obtaining each of the corresponding first and second voltage signals from a simulation of a circuit corresponding to the IC layout diagram (See Para [0056]-[0059], i.e. Metal line structure shown in FIG. 5 is used as an example for simulating the electric path generation).
As per claim 13, Sukharev and Oliva discloses all of the features of claim 11 as discloses above wherein Oliva also discloses wherein the calculating the total FIT rate of the IC layout diagram comprises: calculating cell FIT rates by, for each cell of the plurality of cells, performing a first summing operation on each FIT rate of the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms; and performing a second summing operation on the cell FIT rates corresponding to the plurality of cells (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
As per claim 14, Sukharev and Oliva discloses all of the features of claim 13 as discloses above wherein Oliva also discloses wherein the performing the first summing operation comprises summing a term based on a correlation between first and second TDDB failure mechanisms of the plurality of TDDB failure mechanisms (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
As per claim 15, Sukharev and Oliva discloses all of the features of claim 13 as discloses above wherein Oliva also discloses wherein the calculating the cell FIT rates by performing the first summing operation for each cell of the plurality of cells comprises calculating the corresponding one or more FIT rates based on one or more of a distribution of voltage levels between cells, a distribution of voltage levels over time, a distribution of temperatures between cells, or a distribution of temperatures over time (See Col 6; Lines 29-43, i.e. the average voltage experienced across the devices during the total operation of the circuit, the temperature of the devices).
As per claim 16, Sukharev and Oliva discloses all of the features of claim 11 as discloses above wherein Oliva also discloses wherein the calculating the total FIT rate of the IC layout diagram comprises: calculating TDDB failure mechanism FIT rates by, for each TDDB failure mechanism of the plurality of TDDB failure mechanisms, performing a first summing operation on each FIT rate of the one or more FIT rates of each cell of the plurality of cells; and performing a second summing operation on the TDDB failure mechanism FIT rates corresponding to the plurality of TDDB failure mechanisms (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
As per claim 17, Sukharev and Oliva discloses all of the features of claim 16 as discloses above wherein Oliva also discloses wherein the calculating the TDDB failure mechanism FIT rates by performing the first summing operation for each TDDB failure mechanism of the plurality of TDDB failure mechanisms comprises calculating the corresponding one or more FIT rates based on one or more of a distribution of voltage levels between cells, a distribution of voltage levels over time, a distribution of temperatures between cells, or a distribution of temperatures over time (See Col 6; Lines 29-43, i.e. the average voltage experienced across the devices during the total operation of the circuit, the temperature of the devices).
As per claim 18, Sukharev discloses:
An integrated circuit (IC) design system comprising: a processor; and a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the processor (See Figure 1, i.e. processor & memory) to:
for each cell of a plurality of cells in an IC layout diagram and each time-dependent dielectric breakdown (TDDB) failure mechanism of a plurality of TDDB failure mechanisms (See Para [0003]-[0008], i.e. A robust full-chip assessment technique for low-k TDDB is needed for evaluating the amount of the inter-metal dielectric degradation measured by the leakage current density and the mean time to failure during the circuit design, See Para [0009], i.e. techniques of full-chip assessment of time-dependent dielectric breakdown, See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics):
identify one or more locations of the TDDB failure mechanism in the cell, wherein each location of the one or more locations comprises first and second conductor features separated by a dielectric region (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD);
identify first and second nets comprising the respective first and second conductor features (See Para [0056]-[0069], i.e. Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer…The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics & See Figure 3 and Figure 4, i.e. 410 and 440, and Low-K IMD); and
for each location of the one or more locations, calculate a corresponding failure-in-time (FIT) value of a corresponding one or more FIT values based on respective first and second voltage signals of the first and second nets (See Para [0070]-[0086], i.e. the time-to-failure determination unit 970 determines time-to-failure characteristic values for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns –[prior art base on model of electric path between metal lines, considered as the first and second voltage signals as cited above]);
Sukharev does not teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculate a total FIT rate of the IC layout diagram based on the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells; based on the total FIT rate exceeding a first threshold level, identify a failure location at which a FIT rate of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells exceeds a second threshold level; and modify the IC layout diagram based on the failure location.
However, Oliva teach the limitations: calculating a corresponding failure-in-time (FIT) rate of a corresponding one or more FIT rates; calculate a total FIT rate of the IC layout diagram based on the one or more FIT rates of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells; based on the total FIT rate exceeding a first threshold level, identify a failure location at which a FIT rate of each TDDB failure mechanism of the plurality of TDDB failure mechanisms and each cell of the plurality of cells exceeds a second threshold level; and modify the IC layout diagram based on the failure location (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Oliva into the
teaching of Sukharev because it would allow for designer to determine an accurate
measure of how a circuit affects the reliability of a product in which the circuit is used
(See Col 1; Line 46-57).
As per claim 19, Sukharev and Oliva discloses all of the features of claim 18 as discloses above wherein Oliva also discloses wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to modify the IC layout diagram by replacing a cell of the plurality of cells that comprises the failure location (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
As per claim 20, Sukharev and Oliva discloses all of the features of claim 18 as discloses above wherein Oliva also discloses wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the processor to modify the IC layout diagram by modifying a cell of the plurality of cells that comprises the failure location (See Figure 5, i.e. 311 (computes … failure rates), 313, 315, 317, 319 (modifies the circuit), See Col 6; Line 63 to Col 10; line 40, i.e. compute a scaled failure rate for each of the circuit devices for which an individual failure rate was computed in block 307… individual failure rate is expressed as a FIT rate, the scaled failure rate may be expressed as a scaled FIT rate).
5. Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukharev et al. (U.S. Pub. No. 2017/0286588 A1) in view of Oliva et al. (U.S. Pat. 8,650,527 B2) and further in view of Weir et al. (U.S. Pub. No. 2014/0096098 A1).
As per claim 3, Sukharev and Oliva discloses all of the features of claim 1 as discloses above.
Sukharev and Oliva does not teach the limitations: wherein the calculating each FIT rate of the one or more FIT rates comprises each of the corresponding first and second voltage signals being a direct current (DC) voltage signal.
However, Weir teach the limitations: wherein the calculating each FIT rate of the one or more FIT rates comprises each of the corresponding first and second voltage signals being a direct current (DC) voltage signal (See Para [0033], i.e. eliability simulation may be based on voltage stress of direct current (DC) or alternating current (AC) component induced in an operation of the circuit design).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Weir into the
teaching of Sukharev and Oliva because it would allow for designer to reliability
problems of an integrated circuit based on transistor gate area (See Para [0004]-
[0005]).
As per claim 5, Sukharev and Oliva discloses all of the features of claim 1 as discloses above.
Sukharev and Oliva does not teach the limitations: wherein the calculating each FIT rate of the one or more FIT rates comprises the corresponding first and second voltage signals comprising an alternating current (AC) voltage signal.
However, Weir teach the limitations: wherein the calculating each FIT rate of the one or more FIT rates comprises the corresponding first and second voltage signals comprising an alternating current (AC) voltage signal. (See Para [0033], i.e. eliability simulation may be based on voltage stress of direct current (DC) or alternating current (AC) component induced in an operation of the circuit design).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Weir into the
teaching of Sukharev and Oliva because it would allow for designer to reliability
problems of an integrated circuit based on transistor gate area (See Para [0004]-
[0005]).
Allowable Subject Matter
6. Claims 4 and 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 4, 6, and/or 8, wherein claim 7 depend on claim 6, wherein claim 9 depend on claim 8.
Response to Applicant’s Remarks
8. With respect to Applicant’s remarks, the following are addressed:
Applicant's arguments filed with respect to the claims have been fully considered but they are not persuasive.
Applicant’s remarks (Pages 9-12), argues that prior art does not teach “identifying one or more locations of a time-dependent dielectric breakdown (TDDB) failure mechanism in an integrated circuit (IC) cell, wherein each location of the one or more locations comprises first and second conductor features separated by a dielectric region”.
With respect to Applicant’s remarks, prior art Sukharev is directed to optimizing layout by matching patterns most susceptible to time-dependent dielectric breakdown and applying a fix (See Abstract).
Prior art Sukharev indicated that time-dependent di-electric breakdown (TDDB) occur between two interconnect lines and inter-metal dielectric break downs as a result of long-time application of relatively low electric field (See Para [0003])
[0003] With aggressive technology scaling accompanied by employment of new advanced materials, time-dependent di-electric breakdown (TDDB) is becoming the second leading cause of on-chip interconnect failures after electromigration (EM). In general, the TDDB is a failure mechanism of back-end-of-line interconnects (BEOL). A bridge will form between two interconnect lines when the inter-metal dielectric (IMD) breaks down as a result of long-time application of relatively low electric field. This is different from the hard break-down, which is caused by strong electric field.
Prior art determined the structure that time-dependent di-electric breakdown (TDDB) would occur, include two metal layers and inter-layer dielectric (See Para [0056]).
[0056] Inter-layer dielectric (ILD) and inter-metal dielectric (IMD) are the two types of low-k dielectrics, which represent the isolation between two metal layers and between metal lines in the same layer, respectively. Because the thickness of ILD is generally larger than the metal lines space, the breakdown of dielectrics between metal lines located in the same layer are more vulnerable to breakdown. The reported experiments demonstrate that TDDB failures take place mostly at the interface between the capping layer and the low-k dielectrics.
Prior art Sukharev performs pattern matching of a layout to pre-computed time-to-failure characteristic values and electric attributes of geometric elements (See Para [0070]-[0074]). Because prior art identify structure that would cause TDDB failure and perform pattern matching in order to identify that patterns within a layout that would result in TDDB failure – the prior art therefore perform the identifying one or more locations of a time-dependent dielectric breakdown (TDDB) failure mechanism in an integrated circuit (IC) cell, wherein each location of the one or more locations comprises first and second conductor features separated by a dielectric region, as cited in 1, 11, and 18.
Because the limitations of the claims have been shown to be disclosed by the prior art as cited above, the rejection(s) of the claims are maintained under Sukharev and Oliva as cited above.
Arguments with respect to claims 2, 10, 12-17, 19, and 20 are addressed for the same reason set for claims 1, 11, and 18.
Arguments with respect to claims 3 and 5 are addressed for the same reason set for claims 1, 11, and 18.
Because prior art has been shown to disclose the limitations of the claims as cited above, the rejection of the claims is maintained as cited in the non-final office action. This office action is Final.
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851
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