Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-8 in the reply filed on April 20th, 2026 are acknowledged. Claim 1 has been amended. Claims 3-4 have been cancelled. Claims 9-20 have been withdrawn from consideration. Claims 1-2 and 5-20 are pending.
Action on merits of claims 1-2 and 5-8 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chong (US 2007/0020864, hereinafter as Chong ‘864) in view of Cheng (US 2011/0263092, hereinafter as Cheng ‘092).
Regarding Claim 1, Chong ‘864 teaches a semiconductor structure, comprising:
a substrate (Fig. 6, (10); [0037]), comprising a device cell area (Annotated (A)) and an isolated area (Annotated (B)) located on a periphery of the device cell area;
an isolation structure (14; [0032]), located in the substrate of the isolated area (Annotated (B));
a device gate structure (21; [0033]), located on the substrate of the device cell area; and a source/drain doped layer, embedded into the substrate of the device cell area on two sides of the device gate structure (21), the source/drain doped layer comprising a source/drain bulk layer (36; [0040]), a side wall of the source/drain bulk layer (36) located on an edge of the device cell area (A_Annotated) and the isolation structure (14) being spaced apart (see Fig. 6); wherein
the side wall of the source/drain bulk layer (36) located on the edge of the device cell area (A) has an included angle with the isolation structure (14) and forms a trench with the isolation structure (14), wherein the semiconductor structure further comprises: a metal silicide layer (see para. [0055]), located in the trench and covering a surface of the source/drain bulk layer (36).
Chong ‘864 is shown to teach all the features of the claim with the exception of explicitly the features: “the metal silicide layer and the substrate being spaced apart”.
Cheng ‘092 teaches the metal silicide layer Fig. 3E, (330); [0028]) and the substrate (302; [0012]) being spaced apart (see Fig. 3E).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chong ‘864 by having the metal silicide layer and the substrate being spaced apart in order to enhance carrier mobility and upgrade the device performance and yield (see para. [0027]) as suggested by Cheng ‘092.
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Fig. 6 (Chong ‘864_Annotated)
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Fig. 3E (Cheng ‘092)
Regarding Claim 7, Chong ‘864 teaches a material of the source/drain doped layer comprises SiGe,or SiC (see para. [0040]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chong ‘864 and Cheng ‘092 as applied to claim 1 above, and further in view of Shimamune (US 2014/0361340, hereinafter Shim ‘340).
Regarding Claim 2, Chong ‘864 and Cheng ‘092 are shown to teach all the features of the claim with the exception of explicitly the features: “the side wall of the source/drain bulk layer located on the edge of the device cell area on a side opposite to the isolation structure is a Miller index plane <111>”.
Shim ‘340 teaches the side wall of the source/drain bulk layer (Fig. 5B, (14A/B); [0084]) located on the edge of the device cell area on a side opposite to the isolation structure is a Miller index plane <111> (14c; [0096]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chong ‘864 and Cheng ‘092 by having the side wall of the source/drain bulk layer located on the edge of the device cell area on a side opposite to the isolation structure is a Miller index plane <111> for the purpose of improving operational speed of the transistors (see para. [0002]) as suggested by Shim ‘340.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chong ‘864 and Cheng ‘092 as applied to claim 1 above, and further in view of Liu (US 2019/0393101, hereinafter Liu ‘101).
Regarding Claim 5, Chong ‘864 teaches a groove (or recess (34); [0037]), located in the substrate of the device cell area on the two sides of the device gate structure, the source/drain doped layer (36; [0040]) being located in the groove.
Chong ‘864 and Cheng ‘092 are shown to teach all the features of the claim with the exception of explicitly the features: “a source/drain seed layer, located between the substrate exposed by the groove and the source/drain bulk layer, a doping content of the source/drain seed layer being lower than a doping content of the source/drain bulk layer”.
Liu ‘101 teaches a source/drain seed layer (Fig. 6, (305); [0036]), located between the substrate (300) exposed by the groove (304; [0038]) and the source/drain bulk layer (307; [0045]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chong ‘864 and Cheng ‘092 by having a source/drain seed layer, located between the substrate exposed by the groove and the source/drain bulk layer in order to prevent the stress from releasing from the subsequently formed initial bulk layer (see para. [0040]) as suggested by Liu ‘101.
Chong ‘864, Cheng ‘092 and Liu ‘101 are shown to teach all the features of the claim with the exception of explicitly the feature: “a doping content of the source/drain seed layer being lower than a doping content of the source/drain bulk layer”.
However, it has been held to be within the general skill of a worker in the art to select a doping content of the source/drain seed layer being lower than a doping content of the source/drain bulk layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a doping content of the source/drain seed layer being lower than a doping content of the source/drain bulk layer in order to improve the performance of the semiconductor devices.
Regarding Claim 6, Liu ‘101 teaches the groove is a Σ structure (see Fig. 9).
Further, it has been held to be within the general skill of a worker in the art to select a Σ structure for the groove on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 2, para. [0026]) of Tsai (US 2016/0020275) as evidence. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
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A person of ordinary skills in the art is motivated to select a Σ structure for the groove in order to improve the performance of the semiconductor devices.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chong ‘864 and Cheng ‘092 as applied to claim 1 above, and further in view of Zhang (US 2016/0099339, hereinafter Zhang ‘339).
Regarding Claim 8, Chong ‘864 teaches the substrate comprises a first device cell area for forming a first device (see Fig. 6).
Chong ‘864 and Cheng ‘092 are shown to teach all the features of the claim with the exception of explicitly the features: “a second device cell area for forming a second device, the first device cell area and the second device cell area being isolated by the isolated area; a plurality of device gate structures are located in the first device cell, and a single device gate structure is located in the second device cell area”.
Zhang ‘339 teaches a second device cell area for forming a second device (Fig. 8, (56b); [0045]), the first device cell area and the second device cell area being isolated by the isolated area (26; [0026]); and a single device gate structure is located in the second device cell area (see Fig. 8).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Chong ‘864 and Cheng ‘092 by having a second device cell area for forming a second device, the first device cell area and the second device cell area being isolated by the isolated area in order to increase the carrier mobilities of the PMOS and NMOS transistors (see abstract) as suggested by Zhang ‘339.
Chong ‘864, Cheng ‘092 and Zhang ‘339 are shown to teach all the features of the claim with the exception of explicitly the feature: “a plurality of device gate structures are located in the first device cell”.
However, it has been held to be within the general skill of a worker in the art to select a plurality of device gate structures are located in the first device cell on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. And it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. A person of ordinary skills in the art is motivated to select a plurality of device gate structures are located in the first device cell in order to improve the performance of the semiconductor devices.
Response to Arguments
Applicant’s arguments with respect to claims 1-2 and 5-8, filed on April 20th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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