Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG (Pub. No.: US 2022/0037510) in view of Lille (Patent No.: US 10249683).
Re claim 1, CHENG, Fig. 27 teaches a device structure, comprising:
a first dielectric material layer (138, ¶ [0022]);
a first conductive interconnect structure ([144/142]/140, [0032]) embedded in the first dielectric material layer and comprising a first metallic barrier liner (140) and a first metal fill material (144/142) portion having a top surface within a first horizontal plane, wherein the first metallic barrier liner (140) laterally surrounds the first metal fill material portion (144/142) and has a top surface below the first horizontal plane such that a moat-shaped divot is located between the first metal fill material portion (144/142) and the first dielectric material layer (138);
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a divot-fill conductive portion (150 portion which filled up the divot portion/[D-FwD]) located in the moat-shaped divot and contacting the top surface of the first metallic barrier liner (140);
a second dielectric material layer (118B/148/152) overlying the first dielectric material layer; and
a second conductive interconnect structure (150/152) embedded in the second dielectric material layer (118B/148/152) and contacting at least a segment of the top surface of the first metal fill material portion (144/142), wherein
the second conductive interconnect structure comprises a metal via structure (150/152, [0040]).
CHENG fails to teach a divot-fill dielectric portion, wherein:
the first conductive interconnect structure comprises a bit line of a semiconductor device.
Lille teaches a divot-fill dielectric portion ([D-FwD]/60, FIG. 8C [flip it 90º], col. 24, lines 13-16), wherein:
the first conductive interconnect structure comprises a bit line (90, col. 15, lines 21-30) of a semiconductor device.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the electrical shorting as taught by Lille.
Re claim 2, in the combination, CHENG, Fig. 27 and Lille, FIG. 25 [as shown above] teaches the device structure of Claim 1, wherein a bottom surface of the second conductive interconnect structure (150) is in direct contact with at least the segment of the top surface of the first metal fill material portion (144/142) and is in direct contact with at least a segment of a top surface of the divot-fill dielectric portion [D-FwD].
Re claim 3, in the combination, Lille, FIG. 25 [as shown above] teaches the device structure of Claim 2, wherein the top surface the divot-fill dielectric portion [D-FwD] and the top surface of the first dielectric material layer (32) are located in the first horizontal plane.
Re claim 4, in the combination, Lille, FIG. 25 [as shown above] teaches the device structure of Claim 1, wherein a bottom surface of the second conductive interconnect structure (150) is in contact with a segment of the top surface of the first dielectric material layer (138).
Re claim 5, in the combination, Lille, FIG. 25 [as shown above] teaches the device structure of Claim 1, wherein a periphery of a bottom surface of the second conductive interconnect structure (150) is in contact with at least a segment of the top surface of the first metal fill material portion divot, at least a segment of a top surface of the divot-fill dielectric portion [D-FwD], and a segment of the top surface of the first dielectric material layer (138).
Re claim 6, in the combination, CHENG, Fig. 27 and Lille, FIG. 25 [as shown above] teaches the device structure of Claim 1, wherein the divot-fill dielectric portion has an annular configuration [D-FwD] and laterally surrounds an upper portion of the first metal fill material portion (140).
Re claim 7, in the combination, CHENG, Fig. 27 a [as shown above] teaches the device structure of Claim 1, wherein each sidewall of the first metal fill material portion comprises:
a respective lower sidewall segment (of 144/142) in contact within a respective inner sidewall of the first metallic barrier liner (140); and
a respective upper sidewall segment (of 144/142) in contact with a respective inner sidewall of the divot-fill dielectric portion [D-FwD].
Re claim 8, in the combination, Lille, FIG. 25 [as shown above] teaches the device structure of Claim 1, wherein: vertically-extending portions of the first metallic barrier liner have a first thickness (46); and the divot-fill dielectric portion (60) has the first thickness.
Re claim 11, in the combination, CHENG, Fig. 27 teaches the first metallic barrier liner comprises a titanium layer, a tantalum layer, a titanium nitride layer or a tantalum nitride layer (140, [0034]); and
the first metal fill material comprises copper at an atomic percentage greater than 95 % (144 with completely filled with copper material, [0037]).
Re claim 12, in the combination, CHENG, Fig. 27 [as shown above] teaches the device structure of Claim 1, wherein the divot-fill dielectric portion comprises a downward-protruding divot-fill dielectric portion [D-FwD] of a dielectric diffusion barrier layer (140) overlying the first conductive interconnect structure (140) and the first dielectric material layer (138), and underlying the second dielectric material layer (118B/148/152).
Re claim 13, in the combination, CHENG, Fig. 27 [as shown above] teaches the device structure of Claim 12, wherein the dielectric diffusion barrier layer comprises a silicon nitride layer (140, [0034]), an aluminum nitride layer, a silicon carbonitride layer or a silicon oxynitride layer including nitrogen atoms at a higher atomic percentage than oxygen atoms.
Re claim 14, in the combination, CHENG, Fig. 27 [as shown above] teaches the device structure of Claim 12, wherein:
the dielectric diffusion barrier layer comprises a silicon nitride layer (140, [0034]); and
the device structure further comprises a silicon carbonitride etch stop dielectric layer (152 of CHENG with material 53 of FIG. 6D of Lille) contacting a top surface of the dielectric diffusion barrier layer and contacting a bottom surface of the second dielectric material layer (118B/148/152).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG in view of Lille and further in view of Li (Pub. No.: US 2019/0115421).
Re claim 9, CHENG teaches all the limitation of claim 1.
CHENG fails to teach the limitation of claim 9.
Li teaches wherein the second conductive interconnect structure comprises:
a second metallic barrier liner (22, FIG. 1, ¶ [0036]) having a bottom surface within the first horizontal plane, having a top surface located within a second horizontal plane, and contacting at least a segment of the top surface of the first metal fill material portion (16); and
a second metal fill material portion (24) that is laterally surrounded by the second metallic barrier liner and having a top surface within the second horizontal plane.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching because by removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise as taught by Li, Abstract.
Re claim 10, in the combination, Li, FIG. 1 teaches the device structure of Claim 9, wherein:
the second metallic barrier liner comprises a titanium layer, a tantalum layer, a titanium nitride layer, a tantalum nitride layer, a tungsten nitride layer, or a molybdenum nitride layer (22, [0039]); and
the second metal fill material portion comprises tungsten, cobalt, ruthenium, titanium, tantalum, or molybdenum (24, [0041]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG in view of Lille and further in view of Pachamuthu (Patent No.: US 9478495).
Re claim 15, in the combination, Lille, FIG. 25 [as shown above] further teaches the device structure of Claim 1, further comprising:
a three-dimensional memory device underlying the first dielectric material layer and comprising an alternating stack of insulating layers (32, FIG. 3) and electrically conductive layers (46), a two-dimensional array of memory openings vertically extending through the alternating stack.
CHENG fails to teach a two-dimensional array of memory opening fill structures located in the two-dimensional array of memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; and
a two-dimensional array of contact via structures overlying the three-dimensional memory array and electrically connected to a respective one of the vertical semiconductor channels,
wherein the first conductive interconnect structure is a bit line that is electrically connected to a respective subset of the contact via structures within the two-dimensional array of contact via structures.
Pachamuthu teaches a two-dimensional array of memory opening fill structures located in the two-dimensional array of memory openings (filled up by 88/89) and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel (60602L, FIG. 2F); and
a two-dimensional array of contact via (88/89) structures overlying the three-dimensional memory array and electrically connected to a respective one of the vertical semiconductor channels,
wherein the first conductive interconnect structure is the bit line (88) that is electrically connected to a respective subset of the contact via structures (89) within the two-dimensional array of contact via structures.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of utilizing the enhanced interconnection structure into 3D memory device as taught by Pachamuthu.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHENG in view of Lille and further in view of Wu (Pub. No.: US 2018/0090431).
Re claim 21, in the combination, CHENG, Fig. 27 teaches the device structure of Claim 1, wherein:
the first metal fill material portion of the bit line comprises copper (140, [0034]).
CHENG/Lille fails to teach the metal via structure comprises fluorine containing tungsten that is formed using tungsten hexafluoride precursor.
Wu teaches the metal via structure comprises fluorine containing tungsten that is formed using tungsten hexafluoride precursor (202, Fig. 3B, [0032]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of ultilizing the metal materials such as tungsten manifests critical functions as taught by Wu, [0002].
Moreover, after the combining of CHENG/Lille and Wu would teach the divot-fill dielectric portion separates the first metallic barrier liner of the bit line from the fluorine containing tungsten of the metal via structure to reduce fluorine diffusion and damage to the first metallic barrier liner.
Response to Arguments
Applicant's arguments filed 08/13/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument:
“A. Amendment Overcomes Rejection of Claim 1 over Cheng and Lille
Claim 1 is amended to include the first two elements of claim 11. Amended claim
1 now recites that the first interconnect structure comprises a bit line. The Office Action admits that Cheng and Lille do not teach that the first conductive interconnect structure comprises a bit line of a semiconductor device, as recited in original claim 11. Therefore, even if there was a reason to combine Cheng and Lille (which Applicants do not concede), the rejection of claim 1 over Cheng and Lille is overcome by amendment. Furthermore, Li was applied in the rejection of claims 9 and 10, and does not remedy the deficiencies noted above.
B. No Reason to Combine References To Arrive at Device of Claim 1
Original claim 11 was rejected over a combination of Cheng, Lille and
Pachamuthu. Thus, this rejection will be addressed insofar as it applies to amended claim 1 which includes the elements of claim 11. Even if there was a reason to combine Cheng, Lille and Pachamuthu (which
Applicants do not concede), the combination would not teach all elements of amended claim 1. The Office Action asserts that a moat shaped divot is formed in a gate electrode stack 132 of a field effect transistor 100 of FIG. 27 of Cheng. Specifically, it is alleged that the divot is formed in layers 140 / 142 of the gate stack 132, and that a divot fill conductive layer 150 fills the divot. Conductive layer 150 is a growth promotion layer that is disposed on the gate stack 132 of Cheng.
The Office Action asserts that FIG. 25 of Lille illustrates a divot-fill dielectric portion 60, and that it would have been obvious to substitute the divot fill conductive layer 150 of Cheng with the divot-fill dielectric portion 60 of Lille.
Element 60 of Lille comprises an insulating spacer that is formed at the levels of conductive layers 46 that function as word lines (e.g., gate electrodes). Therefore, both Cheng and Lille disclose divots formed in gate electrodes that are then filled with respective conductive or insulating materials.
However, neither Cheng nor Lille teach forming a divot in a lit line, as now recited in claim 1 as amended.
Pachamuthu was cited for teaching a bit line. Pachamuthu teaches that elements 88 comprise drain contact via structures and elements 89 comprise bit lines in FIG. 18 (see col. 26, lines 53-55 of Pachamuthu). However, neither the drain contact via structures 88 nor the bit lines 89 contain any moat-shaped divots, as recited in amended claim 1.
Therefore, even if there was a reason to combine Pachamuthu with Cheng and Lille (which Applicants do not concede), then one of ordinary skill in the art would at best form divots in the word lines 46 of Pachamuthu, as taught by Lille. However, there would be no reason to form the claimed moat-shaped divot in the bit lines 89 of Pachamuthu because neither Cheng nor Lille provide any reason for forming divots in bit lines, nor any advantage from forming divots in bit lines.” Pages 1-2.
The Examiner respectfully submits that In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, since both CHENG and Lille teach on the first and second conductive interconnect structure, therefore One would be motivated to make such a change to generate the claimed invention with a reasonable expectation of success and yield predictable results, and CHENG, Fig. 27 teaches wherein
the second conductive interconnect structure comprises a metal via structure (150/152, [0040]).
CHENG fails to teach a divot-fill dielectric portion, wherein:
the first conductive interconnect structure comprises a bit line of a semiconductor device.
Lille teaches a divot-fill dielectric portion ([D-FwD]/60, FIG. 8C [flip it 90º], col. 24, lines 13-16), wherein:
the first conductive interconnect structure comprises a bit line (90, col. 15, lines 21-30) of a semiconductor device.
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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