Prosecution Insights
Last updated: April 19, 2026
Application No. 18/359,645

THERMALLY CONDUCTIVE SPACER

Non-Final OA §102§103
Filed
Jul 26, 2023
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandisk Technologies Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
85%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
648 granted / 845 resolved
+8.7% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1-3, 7, 10-12 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PG Pub 2013/0093103, herein after Kim). Regarding claim 1, figure 1 of Kim discloses a semiconductor package, comprising: a printed circuit board (110, ¶ 27); a first stack of semiconductor dies (120); a second stack of semiconductor dies (130); and a thermally conductive spacer (140) provided between the first stack of semiconductor dies and the second stack of semiconductor dies, the thermally conductive spacer comprising: a thermal conductivity feature that moves heat generated by the semiconductor dies adjacent to the thermally conductive spacer away from the adjacent semiconductor dies (¶ 31). Regarding claim 2, figure 1 of Kim discloses a set of dimensions of the thermally conductive spacer are greater than a set of dimensions of at least one semiconductor die associated with the first stack of semiconductor dies. Regarding claim 3, figure 1 of Kim discloses the thermal conductivity feature comprises a thermal conductive material provided on one or more of a top surface of the thermally conductive spacer and a bottom surface of the thermally conductive spacer (¶ 31). Regarding claim 7, figure 1 of Kim discloses one or more tines (145, ¶41) extending from a surface of the thermally conductive spacer to a surface of the PCB. Regarding claim 10, figure 1 of Kim discloses the thermally conductive spacer (140) is comprised of a thermal conductive material (¶ 31). Regarding claim 11, figure 1 of Kim discloses a semiconductor package, comprising: a printed circuit board (PCB)(110, 27); a stack of memory dies (120/130), each memory die of the stack of memory dies having a first set of dimensions (height); and a thermally conductive spacer (140) provided between a first memory die of the stack of memory dies and a second memory die of the stack of memory dies, the thermally conductive spacer having a thermal conductivity feature (¶ 31) and having a second set of dimensions (length) that are larger than the first set of dimensions. Regarding claim 12, figure 1 of Kim discloses the entire claimed invention as noted in the above rejections. Regarding claims 19-20, figure 1 of Kim discloses the entire claimed invention as noted in the above rejections. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim. Regarding claim 9, Kim discloses at least one of the first stack of semiconductor dies and the second stack of semiconductor dies is a stack of memory dies (¶ 35). Kim does not explicitly disclose NAND memory dies. However, it would have been obvious to use NAND memory dies since they are a well known type of memory die for memory devices. Allowable Subject Matter Claims 4-6, 8 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

Jul 26, 2023
Application Filed
Dec 28, 2025
Non-Final Rejection — §102, §103
Apr 09, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604693
METHOD OF MANUFACTURING CHIPS
2y 5m to grant Granted Apr 14, 2026
Patent 12598821
CHIP PACKAGE STRUCTURE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593717
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12581982
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 17, 2026
Patent 12582016
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
85%
With Interview (+8.4%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allow rate.

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