Prosecution Insights
Last updated: August 16, 2026
Application No. 18/359,645

THERMALLY CONDUCTIVE SPACER

Final Rejection §102
Filed
Jul 26, 2023
Priority
Jun 05, 2023 — provisional 63/506,323
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
673 granted / 871 resolved
+9.3% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
892
Total Applications
across all art units

Statute-Specific Performance

§101
3.6%
-36.4% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 871 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 11-12 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PG Pub 2013/0093103, herein after Kim). Regarding claim 11, figure 1 of Kim discloses a semiconductor package, comprising: a printed circuit board (PCB)(110, 27); a stack of memory dies (120/130), each memory die of the stack of memory dies having a first set of dimensions (height); and a thermally conductive spacer (140) provided between a first memory die of the stack of memory dies and a second memory die of the stack of memory dies, the thermally conductive spacer having a thermal conductivity feature (¶ 31) and having a second set of dimensions (length) that are larger than the first set of dimensions. Regarding claim 12, figure 1 of Kim discloses the entire claimed invention as noted in the above rejections. Regarding claims 19-20, figure 1 of Kim discloses the entire claimed invention as noted in the above rejections. Allowable Subject Matter Claims 1-8 and 21-22 are allowed. Regarding claim 1, the closest prior art of record, Kim et al. (US PG Pub 2013/0093103) either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor package, comprising: a printed circuit board (PCB); a first stack of semiconductor dies; a second stack of semiconductor dies; and a thermally conductive spacer provided between the first stack of semiconductor dies and the second stack of semiconductor dies, the thermally conductive spacer comprising: a thermally conductive material; and a thermal conductivity feature that moves heat generated by the semiconductor dies adjacent to the thermally conductive spacer away from the adjacent semiconductor dies”. Claims 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 4/27/2026 have been fully considered but they are not persuasive. Applicants argue that the spacer and chips of Kim have the same size and the spacer is not longer than the semiconductor dies. However, the claims as written do not specify how the first and second set of dimensions are measured. As previously noted in the Office Action of 1/26/2026, the height of the dies is taken as the first set of dimensions and the length of the spacer is taken as the second set of dimensions. Thus, the second set of dimensions is larger than the first set of dimensions as shown in figure 1 of Kim. For at least the aforementioned reasons, the rejections is deemed proper and made final. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jul 26, 2023
Application Filed
Jan 26, 2026
Non-Final Rejection mailed — §102
Apr 09, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Examiner Interview Summary
Apr 27, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707750
IMAGING ELEMENT AND ELECTRONIC APPARATUS
2y 8m to grant Granted Aug 11, 2026
Patent 12708051
SEMICONDUCTOR PACKAGE
2y 4m to grant Granted Aug 11, 2026
Patent 12702037
BONDING APPARATUS, BONDING METHOD, AND COMPUTER READABLE STORAGE MEDIUM
3y 2m to grant Granted Aug 04, 2026
Patent 12696762
POWER SEMICONDUCTOR MODULE COMPRISING AT LEAST ONE POWER SEMICONDUCTOR ELEMENT
3y 7m to grant Granted Jul 28, 2026
Patent 12690489
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
3y 11m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.5%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 871 resolved cases by this examiner. Grant probability derived from career allowance rate.

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