DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 24 November 2025 is acknowledged.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 26 July 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sel et al (US 20180350879 A1), in view of Kaminaga (US 20200035694 A1, hereinafter “Kaminaga”).
Regarding Claim 1 – Sel discloses a semiconductor structure, comprising: an alternating stack of insulating layers (60 Sel [0057] and Fig. 20A) and electrically conductive layers (30 Sel [0057] and Fig. 20A); a memory opening vertically extending through the alternating stack (unnumbered Sel [0141 and Fig. 20A); a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel (45 Sel [0141] and Fig. 20A); and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer (66 Sel [0143] and Fig. 20A), contacting a top surface of a topmost electrically conductive layer within the subset of the electrically conductive layers (Sel [0143] and Top Surface in annotated Fig. 20A).
Sel fails to disclose the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers, and the contact via structures having a topmost surface below a horizontal plane including a topmost surface of the alternating stack.
However, Kaminaga discloses the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers (200 Kaminaga [0217] and Fig. 3), and the contact via structures having a topmost surface below a horizontal plane including a topmost surface of the alternating stack (668 Kaminaga [420] and Fig. 60K).
Kaminaga discloses a similar memory structure to Sel. Kaminaga teaches a stair-stepped alternating stack structure that has contact structures with a topmost surface below the horizontal plane of the topmost surface of the alternating stack for the benefit of high density (Kaminaga [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining Sel and Kaminaga to obtain the benefit of a high density memory structure.
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Regarding Claim 2 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a backside dielectric layer contacting a bottom surface of the bottommost insulating layer (190A Sel [0068] and Fig. 20A), wherein the layer contact via structure vertically extends through the backside dielectric layer (Sel [0095] and Fig. 20A).
Regarding Claim 3 – Sel modified by Kaminaga discloses all the limitations of claim 2.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises: a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (66 Sel [0064] and Fig. 20A); and a plug portion that vertically extends through the backside dielectric layer, adjoined to a bottom end of the via portion, and having a greater lateral extent than the via portion (162C Sel [0057] and Fig. 20A).
Regarding Claim 5 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises: a via portion that vertically extends through the subset of the electrically conductive layers and the subset of the insulating layers (66L Sel [0105] and Fig. 20A); and a plate portion that overlies a horizontal plane including the top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers and has a bottom surface that contacts a segment of the top surface of the topmost electrically conductive layer (66P Sel Fig. 20A).
Regarding Claim 6 – Sel modified by Kaminaga discloses all the limitations of claim 5.
The combination of Sel and Kaminaga further discloses the layer contact via structure further comprises: a metallic barrier liner in direct contact with the segment of the top surface of the topmost electrically conductive layer (166L Sel [0103] and Fig. 13); and a metallic fill material portion that is laterally surrounded by the metallic barrier liner and comprises a horizontally-extending plate portion that is spaced from the top surface of the topmost electrically conductive layer by a horizontally-extending portion of the metallic barrier liner (266L Sel [0103] and Fig. 13).
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Regarding Claim 7 – Sel modified by Kaminaga discloses all the limitations of claim 5.
The combination of Sel and Kaminaga further discloses a stepped dielectric material portion having a horizontal top surface and a stepped bottom surface that contacts the electrically conductive layers and the layer contact via structure (165 Kaminaga [0218] and Fig. 60K).
Regarding Claim 8 – Sel modified by Kaminaga discloses all the limitations of claim 7.
The combination of Sel and Kaminaga further discloses the stepped dielectric material portion is in direct contact with an entirety of a top surface of the plate portion (combination of 165 and 265 Kaminaga [0218], [0230], [0232], and Figs. 57B and 60K), an entirety of all sidewalls of the plate portion, and segments of top surfaces of the electrically conductive layers (Kaminaga Figs. 57B (plan view) and 60K (cross section view)).
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Regarding Claim 9 – Sel modified by Kaminaga discloses all the limitations of claim 7.
The combination of Sel and Kaminaga further discloses the stepped dielectric material portion is in direct contact with sidewalls of the electrically conductive layers and sidewalls of the insulating layers (165 and 265 contact sidewalls of 132, 146, 232, and 246 in Kaminaga Fig. 60K); and each sidewall of the electrically conductive layers that is in direct contact with the stepped dielectric material portion is vertically coincident with a sidewall of a respective underlying insulating layer of the insulating layers (Kaminaga Figs. 57B (plan view) and 60K (cross section view)).
Regarding Claim 10 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a dielectric spacer (64 Sel [0102] and Fig. 13) laterally surrounding a via portion of the layer contact via structure and vertically extending through, and contacting each electrically conductive layer and each insulating layer within the subset of the electrically conductive layers and the subset of the insulating layers (Sel [0102] and Fig. 13).
Regarding Claim 11 – Sel modified by Kaminaga discloses all the limitations of claim 10.
The combination of Sel and Kaminaga further discloses the layer contact via structure comprises a plate portion that laterally extends horizontally (66P in Sel Fig. 20A), and has a bottom surface that contacts a segment of the top surface of the topmost electrically conductive layer within the subset of the electrically conductive layers (Shown as 66L on 30 in upper left of Sel Fig. 13) and contacts an annular top surface of the dielectric spacer (Top surface of 64 in Sel Fig. 13); and the plate portion has a greater lateral extent than the dielectric spacer (Shown as wider than 64 in Sel Fig. 20A).
Regarding Claim 12 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses additional layer contact via structures (additional 66 Sel Fig. 20A) vertically extending through a respective subset of the electrically conductive layers and a respective subset of the insulating layers that includes the bottommost insulating layer of the insulating layers, contacting a top surface of a respective topmost electrically conductive layer within the respective subset of the electrically conductive layers, and having a respective topmost surface below the horizontal plane including the topmost surface of the alternating stack, wherein a total number of electrically conductive layers within the subsets of the electrically conductive layers for the additional layer contact via structures are different among the subsets of the electrically conductive layers (Multiple contact via structures 66 with varying numbers of 30 and 60 between 66P and 162C Sel [0143] and Fig. 20A).
Regarding Claim 13 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses the alternating stack, the memory opening fill structure, and the layer contact via structures are located within a memory die (Sel [0056] and annotated Fig. 1B); and the semiconductor structure further comprises a logic die (integrated driver circuit Sel [0153] and annotated Fig. 1B) that is bonded to the memory die and comprises a peripheral circuit configured to control operation of the memory elements of the memory opening fill structure (Sel [0150]).
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Regarding Claim 14 – Sel modified by Kaminaga discloses all the limitations of claim 1.
The combination of Sel and Kaminaga further discloses a source layer (combination of 112, 114, and 116 Kaminaga [0271] and Fig. 52F) contacting sidewall portion of the vertical semiconductor channel (60 Kaminaga [249] and Fig. 52F); and a source contact via structure (688 Kaminaga [0348] and Fig. 52F) contacting or electrically connected to the source layer (Kaminaga Fig. 52F) and comprising a same set of metallic materials as the layer contact via structure (liner 186A and fill material 186B are common across peripheral region contact via structures 488, array region contact via structures 588, and source contact via structures 688 Kaminaga [0348]).
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sel et al (US 20180350879 A1), in view of Kaminaga (US 20200035694 A1, hereinafter “Kaminaga”), and further in view of Wang et al (US 20210343639 A1, hereinafter “Wang”).
Regarding Claim 4 – Sel modified by Kaminaga discloses all the limitations of claim 3.
The combination of Sel and Kaminaga fails to disclose the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer; and a lateral extent of the plug portion increase with a downward vertical distance from a horizontal plane including a top surface of the backside dielectric layer.
However, Wang discloses the plug portion comprises a tapered sidewall that vertically extends through the backside dielectric layer (318 Wang [0092] and Fig. 25); and a lateral extent of the plug portion increase with a downward vertical distance (away from the active device) from a horizontal plane including a top surface of the backside dielectric layer (Wang Fig. 25).
Wang describes a circuit with a similar via structure to Sel. Wang teaches a tapered via due to the nature of etching via openings in the backside IMD layers after the structure is flipped upside down (Wang [0092]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the backside vias would have a tapered sidewall as a natural consequence of etching via openings in the IMD layers after the structure is flipped upside down.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898