DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on June 27, 2025.
Claims 1 and 4-7 are amended. Claims 2 and 8-20 are canceled. Claims 21-22 have been added. Claims 1, 3-7, and 21-22 are pending. Because claim 14 has been canceled, objections to claim 14 are withdrawn.
Applicant’s amendments to the specification submitted on June 27, 2025 are acknowledged and the objections to the specification are withdrawn.
Claim Objections
3. Claim 3 is objected to because it is dependent on claim 2, which has been canceled. For the purpose of this action, claim 3 will be examined as dependent on claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1, 3-7, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Park, et al, (US 20230154542 A1), hereinafter Park, in view of Maeda, et al (US 20120134210 A1), hereinafter Maeda.
Regarding independent claim 1, Park teaches in FIG. 3B a non-volatile storage apparatus, comprising:
a plurality of bit lines (BL1..BL3);
a plurality of word lines (WL1..WLn);
a source line (CSL);
non-volatile memory cells (MC1..MCn) arranged in NAND strings (NS11..NS33), the NAND strings are grouped into a set of blocks (FIG. 2, 110, BLK1..BLz), each block of the set of blocks includes multiple sub-blocks (sub-blocks shown comprising NS11..NS13, NS21..NS23, and NS31..NS33), each NAND string in a selected block of the set of blocks is connected to the source line and the plurality of word lines (each NAND string is shown connected to CSL and WL1..WLn), each word line of the plurality of word lines is connected to every sub-block of the selected block of the set of blocks (each of WL1..WLn is shown connected to each previously-identified sub-block), each bit line of the plurality of bit lines is connected to NAND strings in every sub-block of each block of the set of blocks (each bit line is shown connected to each previously-identified sub-block), each sub-block includes a bit line side and a source side (each sub-block is shown with string select (BL side) and ground select (source side) transistors), each of the NAND strings includes multiple non-volatile memory cells (MC1..MCn) arranged in series with:3
a first source side select transistor (GSTU) that is positioned in the NAND string closer to the source line than the multiple non-volatile memory cells, a second source side select transistor (GSTD) that is positioned in the NAND string closer to the source line than the first source side select transistor, a first source side GIDL generation transistor (GDT_GSU) that is positioned in the NAND string closer to the source line than the second source side select transistor, and a second source side GIDL generation transistor (GDT_GSD) that is positioned in the NAND string closer to the source line than the first source side GIDL generation transistor (see FIG. 3B for transistor positioning within each string);
a first set of source side select lines each connected to the first source side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., GSLU1 is connected only to the sub-block comprising NS11..NS13);
a second set of source side select lines each connected to the second source side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., GSLD1 is connected only to the sub-block comprising NS11..NS13);
a first set of source side GIDL generation transistor control lines each connected to the first source side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_GSU1 is connected only to the sub-block comprising NS11..NS13);
a second set of source side GIDL generation transistor control lines each connected to the second source side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_GSD1 is connected only to the sub-block comprising NS11..NS13); and
a control circuit (FIG. 2, 120) connected to the non-volatile memory cells.
Park does not teach the control circuit is configured to erase a selected sub-block of a selected block without erasing one or more unselected sub-blocks of the selected block by causing using Gate Induced Drain Leakage ("GIDL") at the source side of the selected sub-block of the selected block while inhibiting GIDL at the source side of the one or more unselected sub-blocks of the selected block by applying an erase voltage to the source line, applying a GIDL enable voltage to GIDL generation transistor control lines of the first set of source side GIDL generation transistor control lines connected to the selected sub-block of the selected block,
applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to the selected sub-block of the selected block,
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of source side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block,
applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to unselected sub- blocks of the selected block, and
applying a selection voltage to the first set of source side select lines and the second set of source side select lines.
Maeda teaches the control circuit (FIG. 10, AR2) is configured to erase a selected sub-block of a selected block (FIG. 10, SB1 of MB; ¶ [0101-0102]) without erasing one or more unselected sub-blocks of the selected block (FIG. 10, SB2 of MB; ¶ [0103]) by causing using Gate Induced Drain Leakage ("GIDL") at the source side of the selected sub-block of the selected block (e.g., via select line SDS21 coupled to SSTr2 of SB1 of MB; ¶ [0102]; see also FIG. 15A) while inhibiting GIDL at the source side of the one or more unselected sub-blocks of the selected block (e.g., via select line SGS22 coupled to SSTr2 of SB2 of MB; ¶ [0103]; see also FIG. 15A) by applying an erase voltage to the source line (FIG. 15A, SL = Vera; ¶ [0102]), applying a GIDL enable voltage to GIDL generation transistor control lines of the first set of source side GIDL generation transistor control lines (FIG. 15A, SGS21 voltage Vera-ΔV; ¶ [0102]) connected to the selected sub-block of the selected block,
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of source side GIDL generation transistor control lines (FIG. 15A, SGS22 voltage Vera’; ¶ [0103]) connected to unselected sub-blocks of the selected block, and
applying a selection voltage to the first set of source side select lines (Maeda FIG. 15A, SGS11 voltage Vmid; ¶ [0102]).
Park as modified by Maeda teaches applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to the selected sub-block of the selected block (Park FIG. 5A, Vgidl; ¶ [0072]; ¶ [0053] teaches the number of ground selection lines, the number of string selection lines, and the number of erase control lines may vary in accordance with an embodiment; ¶ [0058]),
applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to unselected sub- blocks of the selected block (Maeda FIG. 15A, SGS22 voltage Vera’; ¶ [0103]; Park FIG. 3B; ¶ [0053], [0058]), and
applying a selection voltage to the second set of source side select lines (Maeda FIG. 15A, SGS11 and SGS12 voltages Vmid; Park FIG. 3B; ¶ [0053], [0058]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Maeda into the method of Park to include applying a GIDL inhibit voltage to the GIDL-generating transistors of an unselected sub-block while applying a GIDL enable voltage to the GIDL-generating transistors of a selected sub-block in an erase operation. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of selectively erasing one sub-block while not performing the erase operation in a second sub-block (Maeda, Abstract).
Regarding claim 3, Park as modified by Maeda teaches the limitations of claim 1.
Maeda further teaches the GIDL enable voltage is lower in voltage magnitude than the GIDL inhibit voltage and the erase voltage (¶ [0102] teaches erase voltage (Vera) is about 20V and ΔV may be 5-8V, which means GIDL enable voltage (Vera-ΔV) is about 12-15V. ¶ [0103] teaches Vera’ is “substantially identical” to Vera and therefore about 20V. Therefore, GIDL enable voltage (12-15V) is lower in magnitude than the GIDL inhibit voltage (~20V) and the erase voltage (~20V)).
Regarding claim 4, Park as modified by Maeda teaches the limitations of claim 1.
Maeda further teaches in FIG. 10 the control circuit is further configured to erase the selected sub-block of the selected block without erasing one or more unselected sub-blocks of the selected block by also using causing GIDL at the bit line side of the selected sub-block of the selected block (e.g., by applying Vera-ΔV to select line SGD21 coupled to SDTr2 of SB1 of MB; ¶ [0102]; see also FIG. 15A) while inhibiting GIDL at the bit line side of the one or more unselected sub-blocks of the selected block (e.g., by applying Vera’ to select line SGD22 coupled to SDTr2 of SB2 of MB; ¶ [0103]; see also FIG. 15A).
Regarding claim 5, Park as modified by Maeda teaches the limitations of claim 4.
Park further teaches in FIG. 3B each of the NAND strings includes:
a first bit line side select transistor (SSTD) that is positioned in the NAND string closer to the bit line than the multiple non-volatile memory cells;
a second bit line side select transistor (SSTU) that is positioned in the NAND string closer to the bit line than the first bit line side select transistor;
a first bit line side GIDL generation transistor (GDTD) that is positioned in the NAND string closer to the bit line than the second bit line side select transistor; and
a second bit line side GIDL generation transistor (GDTU) that is positioned in the NAND string closer to the bit line than the first bit line side GIDL generation transistor (see FIG. 3B for positioning of transistors within each string).
Regarding claim 6, Park as modified by Maeda teaches the limitations of claim 5.
Park further teaches in FIG. 3B a first set of bit line side select lines each connected to the first bit line side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., SSLD1 is connected to only the sub-block including NS11..NS13);
a second set of bit line side select lines each connected to the second bit line side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., SSLU1 is connected to only the sub-block including NS11..NS13); and
a first set of bit line side GIDL generation transistor control lines each connected to the first bit line side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_SSD1 is connected to only the sub-block including NS11..NS13);
a second set of bit line side GIDL generation transistor control lines each connected to the second source side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_SSU1 is connected to only the sub-block including NS11..NS13).
Regarding claim 7, Park as modified by Maeda teaches the limitations of claim 6.
Maeda further teaches the control circuit is configured to erase the selected sub-block of the selected block without erasing one or more unselected sub-blocks of the selected block by also using GIDL at the bit line side of the selected sub-block of the selected block while inhibiting GIDL at the bit line side of the one or more unselected sub-blocks of the selected block by:
applying the erase voltage to the bit line (FIG. 15A, BL = Vera; ¶ [0102]), applying the GIDL enable voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to the selected sub-block of the selected block (FIG. 15A, SGD21 voltage = Vera-ΔV; ¶ [0102]),
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block (FIG. 15A SGD22 voltage = Vera’; ¶ [0103]), and
applying a selection voltage to the first set of bit line side select lines (FIG. 15A, SGD11 voltage = Vmid).
Park as modified by Maeda further teaches applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to the selected sub-block of the selected block (Maeda, FIG. 15A, SGD21 voltage = Vera-ΔV; ¶ [0102]; Park FIG. 3B; ¶ [0053] teaches the number of ground selection lines, the number of string selection lines, and the number of erase control lines may vary in accordance with an embodiment; ¶ [0058]),
applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block (FIG. 15A SGD22 voltage = Vera’; ¶ [0103]; Park FIG. 3B; ¶ [0053], [0058]), and
applying a selection voltage to the second set of bit line side select lines (FIG. 15A, SGD11 voltage = Vmid; Park FIG. 3B; ¶ [0053], [0058]).
Regarding independent claim 21, Park teaches in FIG. 3B a non-volatile storage apparatus, comprising:
a plurality of bit lines (BL1..BL3);
a plurality of word lines (WL1..WLn);
a source line (CSL);
non-volatile memory cells (MC1..MCn) arranged in NAND strings (NS11..NS33), the NAND strings are grouped into a set of blocks (FIG. 2, 110, BLK1..BLz), each block of the set of blocks includes multiple sub-blocks (sub-blocks shown comprising NS11..NS13, NS21..NS23, and NS31..NS33), each NAND string in a selected block of the set of blocks is connected to the source line and the plurality of word lines (each NAND string is shown connected to CSL and WL1..WLn), each word line of the plurality of word lines is connected to every sub-block of the selected block of the set of blocks (each of WL1..WLn is shown connected to each previously-identified sub-block), each bit line of the plurality of bit lines is connected to NAND strings in every sub-block of each block of the set of blocks (each bit line BL1..BL3 is shown connected to each previously-identified sub-block), each sub-block includes a bit line side and a source side (each sub-block is shown with string select (BL side) and ground select (source side) transistors), each of the NAND strings includes multiple non-volatile memory cells (MC1..MCn) arranged in series with:
a first bit line side select transistor (SSTD) that is positioned in the NAND string closer to the bit line than the multiple non-volatile memory cells, a second bit line side select transistor (SSTU) that is positioned in the NAND string closer to the bit line than the first bit line side select transistor, a first bit line side GIDL generation transistor (GDTD) that is positioned in the NAND string closer to the bit line than the second bit line side select transistor, and a second bit line side GIDL generation transistor (GDTU) that is positioned in the NAND string closer to the bit line than the first bit line side GIDL generation transistor (see FIG. 3B for positioning of transistors within each string);
a first set of bit line side select lines each connected to the first bit line side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., SSLD1 is connected to only the sub-block including NS11..NS13);
a second set of bit line side select lines each connected to the second bit line side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., SSLU1 is connected to only the sub-block including NS11..NS13);
a first set of bit line side GIDL generation transistor control lines each connected to the first bit line side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_SSD1 is connected to only the sub-block including NS11..NS13);
a second set of bit line side GIDL generation transistor control lines each connected to the second bit line side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_SSU1 is connected to only the sub-block including NS11..NS13); and
a control circuit (FIG. 2, 120) connected to the non-volatile memory cells.
Park does not teach a control circuit connected to the non-volatile memory cells, the control circuit is configured to erase a selected sub-block of a selected block without erasing one or more unselected sub-blocks of the selected block using Gate Induced Drain Leakage ("GIDL") at the bit line side of the selected sub-block of the selected block while inhibiting GIDL at the bit line side of the one or more unselected sub-blocks of the selected block by:
applying an erase voltage to the bit line, applying a GIDL enable voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to the selected sub- block of the selected block,
applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to the selected sub-block of the selected block,
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to unselected sub- blocks of the selected block,
applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block, and
applying a selection voltage to the first set of bit line side select lines and the second set of bit line side select lines.
Maeda teaches a control circuit connected to the non-volatile memory cells (FIG. 10, AR2), the control circuit is configured to erase a selected sub-block of a selected block (FIG. 10, SB1 of MB; ¶ [0101-0102]) without erasing one or more unselected sub-blocks of the selected block (FIG. 10, SB2 of MB; ¶ [0103]) using Gate Induced Drain Leakage ("GIDL") at the bit line side of the selected sub-block of the selected block (e.g., via select line SGD21 coupled to SDTr2 of SB1 of MB; ¶ [0102]; see also FIG. 15A) while inhibiting GIDL at the bit line side of the one or more unselected sub-blocks of the selected block (e.g., via select line SGD22 coupled to SDTr2 of SB2 of MB; ¶ [0103]; see also FIG. 15A) by:
applying an erase voltage to the bit line (FIG. 15A, BL = Vera; ¶ [0102]), applying a GIDL enable voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to the selected sub-block of the selected block (FIG. 15A, SGD21 voltage = Vera-ΔV; ¶ [0102]),
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of bit line side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block (FIG. 15A, SGD22 voltage = Vera’; ¶ [0103]),
applying a selection voltage to the first set of bit line side select lines (FIG. 15A, SGD11 voltage = Vmid).
Park as modified by Maeda further teaches applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to the selected sub-block of the selected block (Maeda, FIG. 15A, SGD21 voltage = Vera-ΔV; ¶ [0102]; Park FIG. 3B; ¶ [0053] teaches the number of ground selection lines, the number of string selection lines, and the number of erase control lines may vary in accordance with an embodiment; ¶ [0058]),
applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of bit line side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block (FIG. 15A SGD22 voltage = Vera’; ¶ [0103]; Park FIG. 3B; ¶ [0053], [0058]), and
applying a selection voltage to the second set of bit line side select lines (FIG. 15A, SGD11 voltage = Vmid; Park FIG. 3B; ¶ [0053], [0058]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Maeda into the method of Park to include applying a GIDL inhibit voltage to the GIDL-generating transistors of an unselected sub-block while applying a GIDL enable voltage to the GIDL-generating transistors of a selected sub-block in an erase operation. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of selectively erasing one sub-block while not performing the erase operation in a second sub-block (Maeda, Abstract).
Regarding independent claim 22, Park teaches a method for erasing a non-volatile memory, the non-volatile memory (FIG. 3B) comprising:
a plurality of bit lines (BL1..BL3),
a plurality of word lines (WL1..WLn),
a source line (CSL),
non-volatile memory cells (MC1..MCn) arranged in NAND strings (NS11..NS33), the NAND strings are grouped into a set of blocks (FIG. 2, 110, BLK1..BLz), each block of the set of blocks includes multiple sub-blocks (sub-blocks shown comprising NS11..NS13, NS21..NS23, and NS31..NS33), each NAND string in the selected block of the set of blocks is connected to the source line and the plurality of word lines (each NAND string is shown connected to CSL and WL1..WLn), each word line of the plurality of word lines is connected to every sub-block of the selected block of the set of blocks (each of WL1..WLn is shown connected to each previously-identified sub-block), each bit line of the plurality of bit lines is connected to NAND strings in every sub-block of each block of the set of blocks (each bit line is shown connected to each previously-identified sub-block), each sub-block includes a bit line side and a source side (each sub-block is shown with string select (BL side) and ground select (source side) transistors), each of the NAND strings includes multiple non-volatile memory cells (MC1..MCn) arranged in series with:
a first source side select transistor (GSTU) that is positioned in the NAND string closer to the source line than the multiple non-volatile memory cells, a second source side select transistor (GSTD) that is positioned in the NAND string closer to the source line than the first source side select transistor, a first source side GIDL generation transistor (GDT_GSU) that is positioned in the NAND string closer to the source line than the second source side select transistor, and a second source side GIDL generation transistor (GDT_GSD) that is positioned in the NAND string closer to the source line than the first source side GIDL generation transistor (see FIG. 3B for the positioning of each transistor within each string);
a first set of source side select lines each connected to the first source side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., GSLU1 is connected only to the sub-block comprising NS11..NS13),
a second set of source side select lines each connected to the second source side select transistors of only one sub-block of the sub-blocks of the selected block (e.g., GSLD1 is connected only to the sub-block comprising NS11..NS13),
a first set of source side GIDL generation transistor control lines each connected to the first source side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_GSU1 is connected only to the sub-block comprising NS11..NS13), and
a second set of source side GIDL generation transistor control lines each connected to the second source side GIDL generation transistors of only one sub-block of the sub-blocks of the selected block (e.g., GIDL_GSD1 is connected only to the sub-block comprising NS11..NS13).
Park does not teach the method comprising:
erasing a selected sub-block of a selected block without erasing one or more unselected sub- blocks of the selected block using Gate Induced Drain Leakage ("GIDL") at the source side of the selected sub-block of the selected block while inhibiting GIDL at the source side of the one or more unselected sub-blocks of the selected block.
Maeda teaches the method comprising:
erasing a selected sub-block of a selected block (FIG. 10, SB1 of MB; ¶ [0101-0102]) without erasing one or more unselected sub-blocks of the selected block (FIG. 10, SB2 of MB; ¶ [0103]) using Gate Induced Drain Leakage ("GIDL") at the source side of the selected sub-block of the selected block (e.g., via select line SDS21 coupled to SSTr2 of SB1 of MB; ¶ [0102]; see also FIG. 15A) while inhibiting GIDL at the source side of the one or more unselected sub-blocks of the selected block (e.g., via select line SGS22 coupled to SSTr2 of SB2 of MB; ¶ [0103]; see also FIG. 15A), the erasing comprises:
applying an erase voltage to the source line (FIG. 15A, SL = Vera; ¶ [0102]), applying a GIDL enable voltage to GIDL generation transistor control lines (FIG. 15A, SGS21 voltage Vera-ΔV; ¶ [0102]) of the first set of source side GIDL generation transistor control lines connected to the selected sub-block of the selected block,
applying a GIDL inhibit voltage to GIDL generation transistor control lines of the first set of source side GIDL generation transistor control lines (FIG. 15A, SGS22 voltage Vera’; ¶ [0103]) connected to unselected sub-blocks of the selected block, and applying a selection voltage to the first set of source side select lines (Maeda FIG. 15A, SGS11 voltage Vmid; ¶ [0102]).
Park as modified by Maeda further teaches the erasing comprises:
applying the GIDL enable voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to the selected sub-block of the selected block (Park FIG. 5A, Vgidl; ¶ [0072]; ¶ [0053] teaches the number of ground selection lines, the number of string selection lines, and the number of erase control lines may vary in accordance with an embodiment; ¶ [0058]), applying the GIDL inhibit voltage to GIDL generation transistor control lines of the second set of source side GIDL generation transistor control lines connected to unselected sub-blocks of the selected block (Maeda FIG. 15A, SGS22 voltage Vera’; ¶ [0103]; Park FIG. 3B; ¶ [0053], [0058]), and applying a selection voltage to the second set of source side select lines (Maeda FIG. 15A, SGS11 and SGS12 voltages Vmid; Park FIG. 3B; ¶ [0053], [0058]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Maeda into the method of Park to include applying a GIDL inhibit voltage to the GIDL-generating transistors of an unselected sub-block while applying a GIDL enable voltage to the GIDL-generating transistors of a selected sub-block in an erase operation. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of selectively erasing one sub-block while not performing the erase operation in a second sub-block (Maeda, Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827