DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-8 and 10-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 3, the limitation “testing the first circuit by applying a predetermined voltage to one of the plurality of bonding pads of the first circuit,” [emphasis added] does not appear to have support in the originally filed disclosure. Specifically, the predetermined voltage is understood to be applied to the first conductive pad and not the bonding pads.
Regarding claim 5, the limitations “patterning the second protection layer to form a second cutting lane on the substrate,” and “cutting the substrate along the second cutting lane after forming the second cutting lane,” do not appear to have support in the originally filed disclosure. Specifically, it is noted that, while there is a disclosure of a second protection layer having a second cutting lane, there is no disclosure of how the second cutting lane is formed, nor is there a disclosure of cutting the substrate along the second cutting lane and along the first cutting lane (see [0048] which recites cutting along the first cutting lane or the second cutting lane).
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-8 and 10-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the limitation “testing the first circuit by applying a predetermined voltage to one of the plurality of bonding pads of the first circuit,” is unclear as to what is required by the claim. Specifically, the testing disclosed is understood to be applied to the first conductive pad and not the bonding pads, and therefore it is unclear what applicant intends by applying the voltage to a bonding pad, what applicant intends as the bonding pads, and as to what applicant intends as the relationship between the plurality of bonding pads and the first conductive pad.
Regarding claim 5, the limitation “patterning the second protection layer to form a second cutting lane on the substrate,” is unclear as to what is required by and/or as to what is the proper scope of “patterning.”
Regarding claim 5, the limitation “cutting the substrate along the second cutting lane after forming the second cutting lane,” is unclear as to how it is related to the cutting step recited in claim 1.
Regarding claim 8, the limitation “verifying an electrical connection between the first circuit and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit after forming the connection pattern,” is unclear as to how it is related to the previous recitation of “wherein the second circuit is electrically connected to the first conductive pad of the first circuit” in claim 7. Specifically, the recitation of claim 7 and the appears to require electrical connection, however the recitation of “verifying an electrical connection…” would appear to imply that there may or may not be an electrical connection. Accordingly, it is unclear if an electrical connection is required.
Regarding claim 16, the limitation “verifying an electrical connection between the light emitting element and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit,” is unclear because “an electrical connection” appears to require electrical connection, however the recitation of “verifying an electrical connection…” would appear to imply that there may or may not be an electrical connection. Accordingly, it is unclear if an electrical connection is required.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi et al. (US 20190326336; herein “Xi”) in view of Lin et al. (US 20120187568; herein “Lin”).
Regarding claim 1, Xi discloses in Figs. 2A-G, 3 an related text a method of manufacturing an electronic device, comprising:
providing a substrate (100) having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface;
forming a first circuit (e.g. circuit including T, see [0033]) on the first surface, wherein the first circuit comprises a transistor (T), a plurality of bonding pads (142, see [0046]), a first conductive pad (e.g. 162, see [0047]) and a first passivation layer (e.g. 150/152/170, see [0032] and [0045]), wherein the plurality of bonding pad comprises a first bonding pad (a first one of 142) and a second bonding pad (a second one of 142), the first passivation layer is disposed on the transistor, and the first bonding pad, the second bonding pad and the first conductive pad are disposed on the first passivation layer;
forming a first protection layer (e.g. 190, see [0048]) on the first surface; and
cutting the substrate (see [0066]-[0067]).
Xi does not explicitly disclose
patterning the first protection layer to form a first cutting lane on the substrate, wherein the first cutting lane is a trench exposing the first passivation layer; and
cutting the substrate after forming the first cutting lane.
In the same field of endeavor, Lin teaches in Fig. 5t-u a method of forming a semiconductor device comprising
patterning the first protection layer (248, see [0078]) to form a first cutting lane on the substrate, wherein the first cutting lane is a trench exposing layers below the first protection layer (e.g. trench in 248 after cutting of 248 but before cutting proceeds to layers below; note that while not explicitly shown, as the cutting is performed from the side of the device with layer 248 it is apparent that layer 248 would be cut prior to the layers below 248); and
cutting the substrate after forming the first cutting lane (see Fig. 5u).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by having the first protection layer in place during the cutting, as shown by Lin, in order to protect the underlying structures during subsequent processing steps including the cutting (see Lin [0078]-[0079]). The limitation “wherein the first cutting lane is a trench exposing the first passivation layer,” is therefore taught by the first cutting lane being a trench exposing underlying layers, as shown by Lin, in combination with the layer underlying the first protection layer being the first passivation layer, as shown by Xi.
Regarding claim 17, Xi further discloses wherein the transistor comprises a source electrode and a drain electrode (S and D, see [0035]), and the first conductive pad (142) is disposed on the source electrode and the drain electrode.
Regarding claim 18, Xi further discloses wherein the first bonding pad (first 142), the second bonding pad (second 142) and the first conductive pad (162) are disposed on the same layer (150/152/170).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi in view of Lin, as applied to claim 1, and further in view of Jung et al. (US 20200203235; herein “Jung”).
Regarding claims 3 and 4, Xi does not disclose further comprising:
testing the first circuit by applying a predetermined voltage to one of the plurality of bonding pads of the first circuit;
wherein the testing is performed after forming the first circuit and before forming the first protection layer.
In the same field of endeavor, Jung teaches a method of forming an electronic device comprising
testing the first circuit by applying a predetermined voltage to one of the plurality of bonding pads of the first circuit (see [0089]);
wherein the testing is performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by testing the first circuit by applying a predetermined voltage to one of the plurality of pads of the first circuit (see [0089]), and the testing is performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate, as taught by Jung, in order to determine if the circuit is electrically connected and functioning properly (see [0089]). The limitation “the testing is performed after forming the first circuit and before forming the first protection layer,” is therefore taught by the combination of the testing performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate, as shown by Jung, and the first protection layer 109 of Xi being formed to protect the first circuit while forming the second circuit and before the cutting of the substrate. Additionally, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have the testing before forming the first protection layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Response to Arguments
Applicant's arguments filed 6/17/2026 have been fully considered but are moot in view of the new grounds of rejection presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 8/20/2026
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