DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (the protection layer structure of Fig. 3B) for Group 1, Species A (the opening structure of Fig. 3A) for Group 2, Species B (the test pad structure of Fig. 13) for Group 3, Species A (the insulation layer structure of Fig. 7B) for Group 4, and Species B (the first circuit structure of Fig. 15) for Group 5. in the reply filed on 2/11/2026 is acknowledged.
Claim Objections
Claims 5, 10 and 12 are objected to because of the following informalities: “in a (the) normal direction of the substrate” should be changed to “a (the) direction normal to the substrate.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “wherein the first circuit comprises a transistor, a plurality of pads which comprises a first bonding pad, a second bonding pad, a first conductive pad and a first passivation layer,” is unclear as to which of the elements are required to be in the plurality of pads and which of the elements are required to be merely in the first circuit.
Regarding claim 1, the limitation “the first bonding pad, the second bonding pad and the first conductive pad are respectively disposed on the first passivation layer,” is unclear as to what is required by respectively. Specifically, “respectively” is understood to require sequentially or in a given order, but it is unclear from applicant’s disclosure how the first bonding pad, the second bonding pad and the first conductive pad are disposed sequentially or in a given order.
Regarding claim 1, the limitation “forming a first cutting lane on the substrate,” is unclear as to what is required by the limitation. Specifically, because the claim does not recite any associated structure of the “cutting lane,” the “cutting lane” would be understood to merely require space along which the element is intended to be cut. No cutting step is positively recited, however, and it is therefore unclear what is required by the claim because the limitation indicates no structure a mere intention to perform an unclaimed cutting step is not a defined method step.
Regarding claim 5, the limitation “forming a second cutting lane on the substrate, wherein the first cutting lane overlaps the second cutting lane in a normal direction of the substrate” is unclear as to what is required by the limitation. Specifically, because the claim does not recite any associated structure of the “cutting lane,” the “cutting lane” would be understood to merely require a space along which the element is intended to be cut. No cutting step is positively recited, however, and it is therefore unclear what is required by the claim because the limitation indicates no structure a mere intention to perform an unclaimed cutting step is not a defined method step.
Regarding claim 7, the limitation “making the second circuit electrically connected with the first conductive pad of the first circuit by forming a connection pattern overlapping the side surface, a portion of the first circuit and a portion of the second circuit after forming the second circuit,” is unclear as to what has to occur “after forming the second circuit.”
Regarding claim 8, the limitation “testing an electrical connection between the first circuit and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit after forming the connection pattern,” is unclear as to how it is related to the previous recitation of “making the second circuit electrically connected with the first conductive pad of the first circuit” in claim 7. Specifically, the recitation of claim 7 and the appears to require electrical connection, however the recitation of “testing an electrical connection…” would appear to imply that there may or may not be an electrical connection. Accordingly, it is unclear if an electrical connection is required.
Regarding claim 15, the limitation “removing the first protection layer to expose a first bonding pad and a second bonding pad” is unclear as to how it is related to the first and second bonding pads of claim 1.
Regarding claim 16, the limitation “testing the electrical connection between the light emitting element and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit,” is unclear because “the electrical connection” lacks proper antecedent basis. Additionally, it is unclear because “the electrical connection appears to require electrical connection, however the recitation of “testing the electrical connection…” would appear to imply that there may or may not be an electrical connection. Accordingly, it is unclear if an electrical connection is required.
Regarding claim 16, the limitation “one of a plurality of pads of the second circuit,” is unclear as to how it is related to the “a first bonding pad and a second bonding pad” recited in claim 15.
Regarding claim 18, the limitation “the first bonding pad, the second bonding pad and the first conductive pad are disposed on the same layer” is unclear as to how it is related to the recitation of “the first bonding pad, the second bonding pad and the first conductive pad are respectively disposed on the first passivation layer,” and as to how “the same layer” is related to “the first passivation layer.”
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7, 9-10, and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xi et al. (US 20190326336; herein “Xi”).
Regarding claim 1, Xi discloses in Figs. 2A-G, 3 an related text a method of manufacturing an electronic device, comprising:
providing a substrate (100) having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface;
forming a first circuit (e.g. circuit including T, see [0033]) on the first surface, wherein the first circuit comprises a transistor (T), a plurality of pads which comprises a first bonding pad (a first one of 142, see [0046]), a second bonding pad (a second one of 142), a first conductive pad (e.g. 162, see [0047]) and a first passivation layer (e.g. 150/152/170, see [0032] and [0045]), wherein the first passivation layer is disposed on the transistor, and the first bonding pad, the second bonding pad and the first conductive pad are respectively disposed on the first passivation layer;
forming a first protection layer (e.g. 190, see [0048]) on one of the first surface and the second surface; and
forming a first cutting lane (e.g. region including 18 on the first side of the substrate) on the substrate.
Regarding claim 2, Xi further discloses cutting the substrate (see Fig. 2G-3 and [0067]) along the first cutting lane after forming the first cutting lane.
Regarding claim 5, Xi further discloses
forming a second circuit (e,g. circuit including 320, see [0058]) on the second surface;
forming a second protection layer (e.g. 280, see [0059]) on another one of the first surface and the second surface; and
forming a second cutting lane (e.g. region including 18 on second side of the substrate) on the substrate, wherein the first cutting lane overlaps the second cutting lane in a normal direction of the substrate.
Regarding claim 6, Xi further discloses wherein the first cutting lane and the second cutting lane are different in width (note that one can arbitrarily choose regions of each “lane” such that the claimed limitation is met).
Regarding claim 7, Xi further discloses making the second circuit electrically connected with the first conductive pad of the first circuit by forming a connection pattern (e.g. 400, see [0024]) overlapping the side surface, a portion of the first circuit and a portion of the second circuit after forming the second circuit.
Regarding claim 9, Xi further discloses cutting the substrate (see Fig. 2G-3 and [0067]) along the first cutting lane or the second cutting lane after forming the second cutting lane.
Regarding claim 10, Xi further discloses wherein the first protection layer is disposed on the first surface of the substrate, a maximum distance between the first surface of the substrate and a top surface of the first protection layer (190) is greater than a maximum distance between the first surface of the substrate and a topmost point of the connection pattern (400) in the normal direction of the substrate (see Figs. 2F and 3).
Regarding claim 15, Xi further discloses wherein the first protection layer (190) is disposed on the first surface of the substrate, and
the method further comprises: removing the first protection layer to expose a first bonding pad and a second bonding pad (see Fig. 2G); and
transferring and bonding a light emitting element (140, see [0033]) to the first bonding pad and the second bonding pad.
Regarding claim 16, Xi further discloses testing the electrical connection between the light emitting element and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit after bonding the light emitting element (note that in operation, a voltage will be applied to the second circuit and the light will indicate a connection). Note that although shown by the prior art, the claim limitation “testing…by applying a voltage” is understood as a positively reciting a process step of “applying a voltage” with an intended result of “testing.” The court has held that a clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited. (see MPEP 2111.04)
Regarding claim 17, Xi further discloses wherein the transistor comprises a source electrode and a drain electrode (S and D, see [0035]), and the first conductive pad (142) is disposed on the source electrode and the drain electrode.
Regarding claim 18, Xi further discloses wherein the first bonding pad (first 142), the second bonding pad (second 142) and the first conductive pad (162) are disposed on the same layer (150/152/170).
Claim Rejections - 35 USC § 102/103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by Xi or, in the alternative, under 35 U.S.C. 103 as obvious over Xi in view of Axer (US 5285082; herein “Axer”).
Regarding claim 8, Xi further discloses testing an electrical connection between the first circuit and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit after forming the connection pattern (note that in operation, a voltage will be applied to the second circuit). Note that although shown by the prior art, the claim limitation “testing…by applying a voltage” is understood as a positively reciting a process step of “applying a voltage” with an intended result of “testing.” The court has held that a clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited. (see MPEP 2111.04)
In the alternative, Axer teaches a method of making an electronic device comprising testing an electrical connection by applying a predetermined voltage to one of a plurality of pads (see col. 1 lines 25-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by testing an electrical connection by applying a predetermined voltage to one of a plurality of pads in order to determine incorrectly functioning circuits (see col. 1 lines 25-40). The limitation “testing an electrical connection between the first circuit and the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit after forming the connection pattern” is taught by the combination of testing an electrical connection by applying a predetermined voltage to one of a plurality of pads, as shown by Axer, and the electrical connection being between the first circuit and the second circuit after forming the connection pattern.”
Claim Rejections - 35 USC § 103
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi as applied to claim 1, respectively, and in view of Jung et al. (US 20200203235; herein “Jung”).
Regarding claims 3 and 4, Xi does not disclose further comprising:
testing the first circuit by applying a predetermined voltage to one of the plurality of pads of the first circuit;
wherein the testing is performed after forming the first circuit and before forming the first protection layer.
In the same field of endeavor, Jung teaches a method of forming an electronic device comprising
testing the first circuit by applying a predetermined voltage to one of the plurality of pads of the first circuit (see [0089]);
wherein the testing is performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by testing the first circuit by applying a predetermined voltage to one of the plurality of pads of the first circuit (see [0089]), and the testing is performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate, as taught by Jung, in order to determine if the circuit is electrically connected and functioning properly (see [0089]). The limitation “the testing is performed after forming the first circuit and before forming the first protection layer,” is therefore taught by the combination of the testing performed after forming the first circuit and before forming a second circuit on the second surface and before cutting the substrate, as shown by Jung, and the first protection layer 109 of Xi being formed to protect the first circuit while forming the second circuit and before the cutting of the substrate. Additionally, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have the testing before forming the first protection layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi as applied to claim 7 above and in view of Yokoyama et al. (US 20200135126; herein “Yokoyama”).
Regarding claims 11 and 12, Xi further discloses wherein the first protection layer (190) is disposed on the first surface of the substrate, but does not explicitly disclose further comprising:
forming an insulation layer on the connection pattern after forming the connection pattern;
a maximum distance between the first surface of the substrate and the top surface of the first protection layer is greater than a distance between the first surface of the substrate and the topmost point of the insulation layer in the normal direction of the substrate.
In the same field of endeavor, Yokoyama teaches in Fig. 2 and related text forming an electronic device comprising
forming an insulation layer (36, see [0035]) on the connection pattern after forming the connection pattern;
a maximum distance between the first surface of the substrate and a top surface of the first passivation layer (top surface of 51, see [0044]) is greater than a distance between the first surface of the substrate and the topmost point of the insulation layer in the normal direction of the substrate (hs1 is less than hs3, see [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by forming an insulation layer on the connection pattern after forming the connection pattern and a maximum distance between the first surface of the substrate and a top surface of the first passivation layer is greater than a distance between the first surface of the substrate and the topmost point of the insulation layer in the normal direction of the substrate, as taught by Yokoyama, in order to prevent mechanical damage to the connection pattern (see [0044]). The limitation “a maximum distance between the first surface of the substrate and the top surface of the first protection layer is greater than a distance between the first surface of the substrate and the topmost point of the insulation layer in the normal direction of the substrate,” is therefore taught by “a maximum distance between the first surface of the substrate and a top surface of the first passivation layer is greater than a distance between the first surface of the substrate and the topmost point of the insulation layer in the normal direction of the substrate” as shown by Yokoyama, and the a maximum distance between the first surface of the substrate and the top surface of the first protection layer (190) being greater than the maximum distance between the first surface of the substrate and a top surface of the first passivation layer (150/152/170), as shown by Xi.
Claim(s) 5, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi in view of Yokoyama and Jung.
Regarding claims 5 (second interpretation), 13 and 14, Xi further discloses
forming a second circuit (e,g. circuit including 320, see [0058]) on the second surface;
forming a second cutting lane (e.g. region including 18 on second side of the substrate) on the substrate, wherein the first cutting lane overlaps the second cutting lane in a normal direction of the substrate.
but does not disclose
forming a second protection layer on another one of the first surface and the second surface;
testing the second circuit by applying a predetermined voltage to one of a plurality of pads of the second circuit;
wherein the testing is performed after forming the second circuit and before forming the second protection layer.
In the same field of endeavor, Yokoyama teaches in Fig. 2 and related text forming an electronic device comprising
forming a second protection layer (36, see [0035]) on another one of the first surface and the second surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by forming a second protection layer on another one of the first surface and the second surface, as taught by Yokoyama, in order to prevent mechanical damage to the connection pattern (see [0044]).
In the same field of endeavor, Jung teaches a method of forming an electronic device comprising
testing a first circuit by applying a predetermined voltage to one of a plurality of pads of the first circuit (see [0089]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xi by testing the first circuit by applying a predetermined voltage to one of the plurality of pads of the first circuit, as taught by Jung, in order to determine if the circuit is electrically connected and functioning properly (see [0089]). Further, it would have been obvious to apply a same testing method to the second circuit in order to determine if the second circuit is electrically connected and functioning properly. The limitation “wherein the testing is performed after forming the second circuit and before forming the second protection layer,” is taught by the combination of the testing performed prior to the cutting and forming a connection pattern, as shown by Jung, and the second protection layer of Yokoyama being formed after the forming the connection pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 3/18/2026