DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/20/2026.
Claims 1-20 are pending in this application.
Claims 9-14 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Claim Objection
2. The claim is objected to for the following reason:
In claim 6, and claim 18, the phrase:
“wherein the first and the second transistor are a first and a second nanosheet transistor,”
should be changed to:
-- wherein the first and the secondtransistors are a first and a second nanosheet transistors, --.
Appropriate corrections are required.
Remarks
3. Applicant’s arguments have been fully considered, but are moot in view of the new ground(s) of rejection(s).
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-7, and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 2025/0006803)
Regarding claim 1, Cheng discloses a semiconductor structure comprising:
a first transistor TR1 (see figs. 1, 9-11, 16) having a first source/drain (S/D) region 140 or 140 & 346;
a second transistor TR2 having a second S/D region 240 & 344, the second transistor being stacked on top of the first transistor (see fig. 10B); and
a first S/D contact 194 shared by the first S/D region 140 or 140 & 346 of the first transistor TR1 and the second S/D region 240 & 344 of the second transistor TR2,
wherein the first S/D contact 194 has a first portion (beneath silicide layer 344 of the second S/D region 240 &344) and a second portion (laterally surrounded by the silicide layer 344 and above the silicide layer 344), the first portion being in direct contact with a top surface of the first S/D region 140 or 140 & 346 of the first transistor TR1 and in direct contact with a bottom surface of the second S/D region 240 & 344, and the second portion being in direct contact with an inner sidewall of the second S/D region 240 & 344 of the second transistor TR2 (see figs. 11A, 11B).
Regarding claim 2, Cheng discloses the semiconductor structure of claim 1, further comprising a trench anchor 346 (figs. 10A, 10B) (or, the trench anchor is a recessed portion of the first S/D region 140, i.e., bottom portion of opening O3 shown in fig. 9A, such recessed portion anchors the first S/D contact 194 to the first S/D region 140 or 140 & 346) directly on top of the first S/D region 140 or 140 & 346 of the first transistor TR1, wherein the first portion of the first S/D contact 194 saddles on the trench anchor to be in contact with a top surface and sidewall surfaces of the trench anchor. See figs. 11A, 11B.
Regarding claim 3, Cheng discloses the semiconductor structure of claim 2, wherein the trench anchor 346 comprises epitaxially grown silicon-germanium (SiGe) and is partially embedded in the first S/D region of the first transistor TR1. See figs. 11A, 11B, and para. 0025.
Regarding claim 4, Cheng discloses the semiconductor structure of claim 1, wherein the second portion of the first S/D contact 194 is directly on top of a portion of the first portion of the first S/D contact 194 and in an opening surrounded by the second S/D region 240 & 344 of the second transistor. See figs. 11A, 11B.
Regarding claim 5, Cheng discloses the semiconductor structure of claim 1, wherein the second S/D region 240 & 344 of the second transistor TR2 includes an opening extending from a top surface thereof to the bottom surface thereof, the opening has the inner sidewall, and the inner sidewall is in direct contact with the second portion of the first S/D contact 194. See figs. 9-11.
Regarding claim 6, Cheng discloses the semiconductor structure of claim 1, wherein the first and the second transistors TR1, TR2 are a first and a second nanosheet transistors, further comprising a dielectric insulating layer 117 separating the first transistor TR1 from the second transistor TR2. See fig. 11A, and para. 0030.
Regarding claim 7, Cheng discloses the semiconductor structure of claim 1, wherein the top surface of the first S/D region of the first transistor has a V-shape and a bottom surface of the first S/D region of the first transistor has an inverted V-shape. See fig. 1.
Regarding claim 15, Cheng discloses a semiconductor structure comprising:
a first transistor TR1 (see figs. 1, 9-11, 16) having a first and a third source/drain (S/D) region 140 or 140 & 346;
a second transistor TR2 having a second and a fourth S/D region 240 & 344 (fig. 10B), the second transistor TR2 being stacked on top of the first transistor and having the second S/D region 240 & 344 above the first S/D region 140 of the first transistor TR1 and the fourth S/D region 240 & 344 above the third S/D region 140 of the first transistor TR1;
a trench anchor 346 (figs. 10A, 10B) (or, the trench anchor is a recessed portion of the first S/D region 140, i.e., bottom portion of opening O3 shown in fig. 9A, such recessed portion anchors the first S/D contact 194 to the first S/D region 140 or 140 & 346) directly on top of the first S/D region 140 or 140 & 346; and
a first S/D contact 194 shared by the first S/D region 140 or 140 & 346 and the second S/D region 240 & 344,
wherein the first S/D contact 194 has a first portion (beneath silicide layer 344 of the second S/D region 240 & 344) and a second portion (laterally surrounded by the silicide layer 344 and above the silicide layer 344), the first portion being in direct contact with a top surface of the first S/D region 140 or 140 & 346, saddling on the trench anchor 346 (or the recessed portion of the first S/D 140), and in direct contact with a bottom surface of the second S/D region 240 & 344, and the second portion being directly on top of a portion of the first portion, through the second S/D region 240 & 344, and completely surrounded horizontally by the second S/D region 240 & 344 (see fig. 1, fig. 11B).
Regarding claims 16, and 17-19, Cheng discloses the semiconductor structure comprising all claimed limitations. See the rejections of claims 3, and 5-7, respectively.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 8, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2025/0006803) in view of Lin et al. (US 2022/0216340).
Regarding claim 8, and 20, Cheng discloses the semiconductor structure comprising all claimed limitations, as discussed above, and further comprising a second S/D contact 192A (fig. 11A) contacting a top surface of a fourth S/D region 240 of the second transistor TR2.
Cheng fails to disclose a first backside S/D contact contacting a bottom surface of a third S/D region of the first transistor.
Lin discloses a semiconductor structure, shown in figure 20, comprising a first transistor 300 (para. 0037) and a second transistor 400 stacked on top of the first transistor 300, and a first backside S/D contact 286 contacting a bottom surface of a third S/D region 228-1 of the first transistor 300.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Cheng to further comprise a backside S/D contact contacting the bottom surface of the thirst S/D region of the first transistor, as that taught by Lin, in order to provide further access to the first transistor and/or the semiconductor structure, thereby to increase the performance of the structure.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 6:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/Dao H Nguyen/
Primary Examiner, Art Unit 2818
July 28, 2026
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