DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 01/08/2026.
Claims 1-20 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, claims 1-8, and 15-20, is acknowledged.
Claims 9-14 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 07/27/2023, and 10/17/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objection
4. The claim is objected to for the following reason:
In claim 15, line 2 recites feature “a first and a second source/drain (S/D) region”, and line 3 recites “a second and a fourth S/D region”. It is unclear whether the “a second source/drain (S/D) region” in line 2 and the “a second ... S/D region” in line 3 are the same or different.
It is believed that such feature in line 2 should be changed to and/or read as -- “a first and a third source/drain (S/D) region -- .
In claim 15, line 5, the limitation “the third S/D region” lacks an antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alaan et al. (US 2023/0187509)
Regarding claim 1, Alaan discloses a semiconductor structure comprising:
a first transistor 101 (see fig. 1) having a first source/drain (S/D) region 108 & 122;
a second transistor 103 having a second S/D region 110 &112, the second transistor 103 being stacked on top of the first transistor 101; and
a first S/D contact 120 shared by the first S/D region 108 & 122 of the first transistor 101 and the second S/D region 110 & 112 of the second transistor 103, wherein the first S/D contact 120 has a first portion (beneath the second source/drain region 110 & 112) and a second portion (on the sides and above the second source/drain region 110 & 112), the first portion being in direct contact with a top surface of the first S/D region 108 & 122 of the first transistor 101 and in direct contact with a bottom surface of the second S/D region 110 & 112, and the second portion being in direct contact with an inner sidewall of the second S/D region 110 & 112 of the second transistor 103.
Regarding claim 4, Alaan discloses the semiconductor structure of claim 1, wherein the second portion of the first S/D contact 120 is directly on top of a portion of the first portion of the first S/D contact. See fig. 1.
Regarding claim 5, Alaan discloses the semiconductor structure of claim 1, wherein the second S/D region 110, 112 of the second transistor 103 includes an opening (having width W1) extending from a top surface thereof to the bottom surface thereof, the opening has the inner sidewall, and the inner sidewall is in direct contact with the second portion of the first S/D contact 120. See fig. 1.
Regarding claim 6, Alaan discloses the semiconductor structure of claim 1, wherein the first and the second transistor 101, 103 are a first and a second nanosheet transistor, further comprising a dielectric insulating layer 116 separating the first transistor 101 from the second transistor 103.
7. Claims 1-3, 6, 8, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2022/0216340)
Regarding claim 1, Lin discloses a semiconductor structure comprising:
a first transistor 300 having a first source/drain (S/D) region 228-2 (see fig. 20);
a second transistor 400 having a second S/D region 248-2, the second transistor 400 being stacked on top of the first transistor 300; and
a first S/D contact 275 & 278 (filling trench 272, figs. 16, 17) shared by the first S/D region 228-2 of the first transistor 300 and the second S/D region 248-2 of the second transistor 400, wherein the first S/D contact 275 & 278 has a first portion (surrounded by separation layer 242; see figs. 10, 16, and para. 0025) and a second portion (on and surrounded by the second S/D 248-2), the first portion being in direct contact with a top surface of the first S/D region 228-2 of the first transistor 300 (along interfacing line between the first S/D contact 275 & 278 and the top surface of the first S/D region 228-2) and in direct contact with a bottom surface of the second S/D region 248-2 (along interfacing line between the S/D contact 275 & 278 and the bottom surface of the second S/D region 248-2), and the second portion being in direct contact with an inner sidewall 274 (fig. 17) of the second S/D region 248-2 of the second transistor 400.
Regarding claim 2, Lin discloses the semiconductor structure of claim 1, further comprising a trench anchor 275 (fig. 17) directly on top of the first S/D region 228-2 of the first transistor 300, wherein the first portion of the first S/D contact 278 saddles on the trench anchor 275 to be in (at least electrical) contact with a top surface and sidewall surfaces of the trench anchor 275.
Regarding claim 3, Lin discloses the semiconductor structure of claim 2, wherein the trench anchor 275 comprises epitaxially grown silicon-germanium (SiGe) and is partially embedded in the first S/D region of the first transistor. See fig. 17, and para. 0014, 0015.
Regarding claim 6, Lin discloses the semiconductor structure of claim 1, wherein the first and the second transistor 300, 400 are a first and a second nanosheet transistor, further comprising a dielectric insulating layer 242 separating the first transistor 300 from the second transistor 400. See figs. 9, 17.
Regarding claim 8, Lin discloses the semiconductor structure of claim 1, further comprising a second S/D contact 276 contacting a top surface of a fourth S/D region 248-1 of the second transistor 400, and a first backside S/D contact 286 contacting a bottom surface of a third S/D region 228-1 of the first transistor 300. See fig. 20.
Regarding claim 15, Lin discloses a semiconductor structure comprising:
a first transistor 300 having a first and a third source/drain (S/D) region 228-2, 228-1, respectively (see fig. 20);
a second transistor 400 having a second and a fourth S/D region 248-2, 248-1, respectively, the second transistor 400 being stacked on top of the first transistor 300 and having the second S/D region 248-2 above the first S/D region 228-2 of the first transistor 300 and the fourth S/D region 248-1 above the third S/D region 228-1 of the first transistor 300;
a trench anchor 275 (fig. 17) directly on top of the first S/D region 228-2; and
a first S/D contact 278 shared by the first S/D region 228-2 and the second S/D region 248-2,
wherein the first S/D contact 278 has a first portion (surrounded by separation layer 242; see figs. 10, 16, and para. 0025) and a second portion (on and surrounded by the second S/D 248-2), the first portion being in direct contact with a top surface of the first S/D region 228-2, saddling on the trench anchor 275, and in direct (at least electrical) contact with a bottom surface of the second S/D region 248-2, and the second portion being directly on top of a portion of the first portion.
Regarding claim 16, Lin discloses the semiconductor structure of claim 15, wherein the trench anchor comprises epitaxially grown silicon-germanium (SiGe) and is partially embedded in the first S/D region of the first transistor. See fig. 17, and para. 0014, 0015.
Regarding claim 17, Lin discloses the semiconductor structure of claim 15, wherein the second S/D region 248-2 of the second transistor 400 includes an opening extending from a top surface thereof to the bottom surface thereof, the opening has an inner sidewall, and the inner sidewall is in direct contact with the second portion of the first S/D contact 278. See figs. 16, 17.
Regarding claim 18, Lin discloses the semiconductor structure of claim 15, wherein the first and the second transistor are a first and a second nanosheet transistor, further comprising a dielectric insulating layer 242 between the first transistor 300 and the second transistor 400. See figs. 9, 17.
Regarding claim 20, Lin discloses the semiconductor structure of claim 15, further comprising a second S/D contact 276 contacting a top surface of the fourth S/D region 248-1 of the second transistor 400, and a first backside S/D contact 286 contacting a bottom surface of the third S/D region 228-1 of the first transistor 300. See fig. 20.
Claim Rejections - 35 U.S.C. § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Alaan et al. (US 2023/0187509) in view of Chouksey et al. (US 2022/0199771)
Regarding claim 7, Alaan discloses the semiconductor structure of claim 1, comprising all claimed limitations, as discussed above, except for wherein the top surface of the first S/D region of the first transistor has a V-shape and a bottom surface of the first S/D region of the first transistor has an inverted V-shape.
Chouksey discloses a semiconductor structure, shown in fig. 1, comprising transistors 106A, 106B comprising source/drain (S/D) region 114B, wherein the top surface of the S/D region 114B of the transistor has a V-shape and a bottom surface of the first S/D region 114B of the first transistor has an inverted V-shape.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Alaan so that the S/D regions would have V-shape and inverted V-shape, as that/those taught by Chouksey to obtain a structure with lower power and high performance. See para. 0023 of Chouksey.
10. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0216340) in view of Chouksey et al. (US 2022/0199771)
Regarding claim 19, Lin discloses the semiconductor structure of claim 15, comprising all claimed limitations, as discussed above, except for wherein the top surface of the first S/D region of the first transistor has a V-shape and a bottom surface of the first S/D region of the first transistor has an inverted V-shape.
Chouksey discloses a semiconductor structure, shown in fig. 1, comprising transistors 106A, 106B comprising source/drain (S/D) region 114B, wherein the top surface of the S/D region 114B of the transistor has a V-shape and a bottom surface of the first S/D region 114B of the first transistor has an inverted V-shape.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Lin so that the S/D regions would have V-shape and inverted V-shape, as that/those taught by Chouksey to obtain a structure with lower power and high performance. See para. 0023 of Chouksey.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 February 19, 2026