Prosecution Insights
Last updated: July 17, 2026
Application No. 18/359,976

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Final Rejection §102§103§112
Filed
Jul 27, 2023
Priority
Jul 29, 2022 — JP 2022-121410
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsuboshi Diamond Industrial Co. Ltd.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
824 granted / 963 resolved
+17.6% vs TC avg
Minimal -37% lift
Without
With
+-37.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
47 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 963 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the amendment filed on 03/09/26. Claims 1-4, 6-16 are pending. Claims 8-10 are withdrawn and claims 11-16 are newly added. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-4, 6, 7, and 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1, line 8, it is indefinite where the first metal layer is exposed on a side surface of the metal layer. In claim 1, lines 9-11, it is indefinite that the metal layer has a protruding portion on the main surface as it relates to the first metal layer. Specifically, the first metal layer is exposed on what side surface and how is the protrusion portion included in the main surface of the first metal layer? For purpose of examination on the merits the examiner will consider that the first metal layer is the protruding portions extends to make one round along the outer peripheral edge on the main surface. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 4, 6-11, and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kashiwazaki (US PGPub 2016/0254160, hereinafter referred to as “Kashiwazaki”). Kashiwazaki discloses the semiconductor device as claimed. See figures 1-19 and corresponding text, where Kashiwazaki teaches, in claim 1, a semiconductor device comprising: a semiconductor substrate (2); and a metal layer (7) disposed on a surface of the semiconductor substrate (2), wherein the metal layer (7) includes a first metal layer and a second metal layer ([0059-0061]), the second metal layer covers a surface of the first metal layer and has a higher solder wettability than the first metal layer, the second metal layer is exposed on a main surface of the metal layer, the first metal layer is exposed on a side surface of the metal layer ([0058-0060]), the metal layer (7) has a protruding portion (2f) on the main surface, the protruding portion (2f) extends to make one round along an outer peripheral edge of the main surface (figures 1 and 5; [0056]), the first metal layer includes a titanium layer covering the surface of the semiconductor substrate and a nickel layer covering a surface of the titanium layer, and the second metal layer is a gold layer ([0059-0061]). Kashiwazaki teaches, in claim 3, wherein a height of the protruding portion is 1/2 or more of a thickness of the metal layer (figure 10; [0081]). Kashiwazaki teaches, in claim 4, wherein a side surface of the semiconductor substrate is a cleavage plane (figures 13-15; [0083-0093]). Kashiwazaki teaches, in claim 6, wherein the protruding portion has undulations along the outer peripheral edge of the main surface (figure 5; [0069-0070]). Kashiwazaki teaches, in claim 7, wherein the protruding portion is intermittently formed along the outer peripheral edge of the main surface (figure 5; [0069-0070]). Kashiwazaki teaches, in claim 11, wherein in a portion of an outer peripheral end of the protruding portion, the nickel layer and the titanium layer are not covered with the gold layer ([0060-0061], [0069-0070]). Kashiwazaki teaches, in claim 13, wherein a height of the protruding portion is 1/2 or more of a thickness of the metal layer (figure 10; [0081]). Kashiwazaki teaches, in claim 14, wherein the protruding portion protrudes to restrict solder on the main surface from spreading to a side surface of the semiconductor substrate (figure 5; [0068-0069]). Kashiwazaki teaches, in claim 15, wherein the protruding portion is formed along a scribe line (figures 13-15; [0083-0093]) Kashiwazaki teaches, in claim 16, wherein the protruding portion is a ridge line in which the metal layer is plastically deformed (figures 13-15; [0083-0093]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashiwazaki (US PGPub 2016/0254160, hereinafter referred to as “Kashiwazaki”) as applied to claim 1 above. Kashiwazaki discloses the semiconductor device substantially as claimed. See the rejection above. However, Kashiwazaki fails to explicitly teach, in claim 2, wherein the first metal layer is exposed at an outer peripheral end of the protruding portion with a width of 1µm or more. Kashiwazaki teaches, in claim 2, teaches that the recess (2f) (implied protruding portions) by reducing the stress in the layer of the solder material stops cracks within the layer ([0067-0070], the examiner views that width can be adjusted for the purpose of reducing the stress in the layer of the solder material). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the first metal layer is exposed at an outer peripheral end of the protruding portion with a width of 1µm or more, in the device of Kashiwazaki, according to the teachings of Kashiwazaki, with the motivation of preventing cracks within the solder layer resulting in an improvement in the reliability of the semiconductor device. In addition, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007). Kashiwazaki fails to explicitly teach, in claim 12, wherein a width of the portion of the outer peripheral end of the protruding portion is about 2 µm. Kashiwazaki teaches, in claim 12, teaches that the recess (2f) (implied protruding portions) by reducing the stress in the layer of the solder material stops cracks within the layer ([0067-0070] the examiner views that width can be adjusted for the purpose of reducing the stress in the layer of the solder material). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein a width of the portion of the outer peripheral end of the protruding portion is about 2 µm, in the device of Kashiwazaki, according to the teachings of Kashiwazaki, with the motivation of preventing cracks within the solder layer resulting in an improvement in the reliability of the semiconductor device. In addition, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007). Response to Arguments Applicant’s arguments with respect to claim(s) 1-4, 6, 7, and 11-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 May 26, 2026 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jul 27, 2023
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §102, §103, §112
Mar 05, 2026
Applicant Interview (Telephonic)
Mar 05, 2026
Examiner Interview Summary
Mar 09, 2026
Response Filed
Jun 16, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677449
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
4y 1m to grant Granted Jul 07, 2026
Patent 12672498
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
4y 11m to grant Granted Jun 30, 2026
Patent 12672367
SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
2y 9m to grant Granted Jun 30, 2026
Patent 12667003
LIGHT-EMITTING PANEL, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE
3y 11m to grant Granted Jun 23, 2026
Patent 12648440
METHOD FOR MANUFACTURING DOUBLE-SIDED COOLING TYPE POWER MODULE AND DOUBLE-SIDED COOLING TYPE POWER MODULE
4y 2m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
48%
With Interview (-37.1%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 963 resolved cases by this examiner. Grant probability derived from career allowance rate.

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