DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 05/22/2026.
Applicant’s amendments filed 05/22/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1 and 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 18, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0310833 to Shin et al. (hereinafter Shin).
With respect to claim 1, Shin discloses a semiconductor device (e.g., GaN high electron mobility transistor (HEMT), see the annotated Fig. 6 below) (Shin, Figs. 6-7, ¶0002, ¶0005-¶0016, ¶0033-¶0049, ¶0059-¶0065), comprising:
a channel layer (20, GaN) (Shin, Fig. 6, ¶0034-¶0035, ¶0037, ¶0059) over a semiconductor substrate (11);
a barrier layer (30, AlGaN) (Shin, Fig. 6, ¶0039, ¶0059) over the channel layer (20); and
a gate layer (40, p-GaN) (Shin, Fig. 6, ¶0044, ¶0059) over the barrier layer (30), the gate layer (40, p-GaN) being doped with a dopant (e.g., magnesium (Mg)), wherein:
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a first region (e.g., 31/33/32, directly under the gate layer 40) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) in the barrier layer (30) overlies a channel region in the channel layer (20) and underlies the gate layer (40, p-GaN), the first region (31/33/32) having a first concentration (e.g., with maximum concentration about 1E+19 atom/cm3 in the region 33, as shown in Fig. 7) of the dopant (Mg), wherein the barrier layer (30) comprises a first thickness (e.g., a total thickness of 31/33/32 barrier layer under the gate layer 40) in the first region; and
a second region (e.g., a region of the first barrier layer 31, laterally adjacent the first region 31/33/32 under the gate layer 40) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) in the barrier layer (30) laterally disposed from the first region (e.g., the first region 31/33/32 directly under the gate layer 40), the second region (e.g., a region of the first barrier layer 31, laterally adjacent the first region 31/33/32 under the gate layer 40) having a second concentration (e.g., less than 1E+19 atom/cm3) of the dopant (Mg) that is less than the first concentration (e.g., about 1E+19 atom/cm3 in the region 33 of first region 31/33/32 under the gate layer 40), wherein the barrier layer (30) comprises a second thickness (e.g., a thickness of the first barrier layer 31) in the second region (e.g., the region of the first barrier layer 31, laterally adjacent the first region 31/33/32 under the gate layer 40) that is less than the first thickness (e.g., a total thickness of 31/33/32 barrier layer under the gate layer 40).
Regarding claim 3, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the dopant (e.g., magnesium (Mg)) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) is a p-type dopant.
Regarding claim 4, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the dopant (e.g., magnesium (Mg)) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) includes magnesium.
Regarding claim 5, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the first concentration is greater than 1×1016 cm-3 (e.g., maximum Mg concentration in the first barrier region 31/33/32 is about 1E+19 atom/cm3, as shown in Fig. 7, that is greater than 1×1016 cm-3) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 6, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the second concentration is less than 1×1019 cm-3 (e.g., the Mg concentration in the second region 31 is less than 1×1019 cm-3, as shown in Fig. 7) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 7, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein: the channel layer (20, GaN) (Shin, Figs. 6-7, ¶0037, ¶0059) includes gallium nitride (GaN); the barrier layer (30, AlGaN) (Shin, Figs. 6-7, ¶0039, ¶0059) includes aluminum gallium nitride (AlGaN); and the gate layer (40, p-GaN) includes magnesium doped gallium nitride (GaN:Mg) (Shin, Figs. 6-7, ¶0044, ¶0059).
With respect to claim 18, Shin discloses a semiconductor device (e.g., GaN high electron mobility transistor (HEMT), see the annotated Fig. 6 above) (Shin, Figs. 6-7, ¶0002, ¶0005-¶0016, ¶0033-¶0049, ¶0059-¶0065), comprising:
a GaN channel layer (20, GaN) (Shin, Fig. 6, ¶0034-¶0035, ¶0037, ¶0059) over a semiconductor substrate (11);
an AlGaN barrier layer (30, AlGaN) (Shin, Fig. 6, ¶0039, ¶0059) over the GaN channel layer (20); and
a doped GaN gate layer (40, p-GaN) (Shin, Fig. 6, ¶0044, ¶0059) on the AlGaN barrier layer (30);
a drain contact (62) (Shin, Fig. 6, ¶0043, ¶0059) contacting the AlGaN barrier layer (30), wherein:
the doped GaN gate layer (40) includes a p-type dopant (magnesium (Mg)) (Shin, Fig. 6, ¶0044, ¶0059);
a first portion (e.g., 31/33/32, directly under the gate layer 40) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) of the AlGaN barrier layer (30) under the doped GaN gate layer (40, p-GaN) includes a first concentration of the p-type dopant (e.g., maximum Mg concentration about 1E+19 atom/cm3 in the region 33, as shown in Fig. 7), wherein the first portion of the AlGaN barrier layer (30) comprises a first thickness (e.g., a total thickness of 31/33/32 barrier layer under the gate layer 40); and
a second portion (e.g., a region of the first barrier layer 31, laterally adjacent the first portion 31/33/32 under the gate layer 40) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) of the AlGaN barrier layer (30) between the doped GaN gate layer (40) and the drain contact (62) includes a second concentration (e.g., a region of the first barrier layer 31 has Mg concentration less than 1E+19 atom/cm3, as shown in Fig. 7) of the p-type dopant (Mg) less than the first concentration (e.g., about 1E+19 atom/cm3 in the region 33 of first portion 31/33/32 under the gate layer 40), wherein the second portion of the AlGaN barrier layer (30) between the doped GaN gate layer (40) and the drain contact (62) comprises a second thickness (e.g., a thickness of the first barrier layer 31) that is less than the first thickness (e.g., a total thickness of 31/33/32 barrier layers under the gate layer 40).
Regarding claim 20, Shin discloses the semiconductor device of claim 18. Further, Shin discloses the semiconductor device, wherein: the first portion (31/32/33) of the AlGaN barrier layer (30) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) overlies a channel region in the GaN channel layer (20); and the second portion (31) of the AlGaN barrier layer includes an access region (e.g., extending between the gate region and the drain region) in the AlGaN barrier layer (30).
Regarding claim 21, Shin discloses the semiconductor device of claim 18. Further, Shin discloses the semiconductor device, wherein the p-type dopant in the first portion (31/32/33) of the AlGaN barrier layer (30) (Shin, Figs. 6-7, ¶0059, ¶0061-¶0063) extends from an interface between the doped GaN gate layer (40) and the AlGaN barrier layer (30) toward the GaN channel layer (20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0310833 to Shin in view of Miyoshi et al. (US Patent No. 8,008,689, hereinafter Miyoshi).
Regarding claim 2, Shin discloses the semiconductor device of claim 1. Further, Shin does not specifically disclose the semiconductor device, wherein the first concentration is an order of magnitude or more greater than the second concentration.
However, Shin teaches that by lowering the impurity concentration of the second region (e.g., the first barrier layer 31) close to the p-GaN gate layer (40) (Shin, Figs. 6-7, ¶0062), a HEMT device is capable of reducing or preventing a gate leakage current caused by impurity diffusion into the p-type gate layer (40) and has stable normally-off characteristics.
Further, Miyoshi teaches forming a HEMT device (Miyoshi, Figs. 1B, 2A, 4, Col. 1, lines 9-11; Col. 2, lines 10-50; Col. 4, lines 22-45; Col. 5, lines 9-12; Col. 6, lines 2-4) comprising p-type region (5) in the barrier layer (4) immediately under the gate (7) and having an Mg-doping concentration of about 5×1019 cm-3 (Miyoshi, Figs. 1B, 2A, 4, Col. 5, lines 9-12), to provide normally-off HEMT having low on-resistance and a high threshold voltage.
Thus, a person of ordinary skill in the art would recognize that by forming the first region of the barrier layer under the gate having higher Mg-doping concentration of about 5×1019 cm-3 (as taught by Miyoshi), and by lowering the impurity concentration (e.g., to about 5×1018 cm-3) of the second region (e.g., as taught by Shin in Fig. 7), the first concentration would be an order of magnitude or more greater than the second concentration.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming the first region of the barrier layer immediately under the gate having higher Mg-doping concentration of about 5×1019 cm-3 as taught by Miyoshi, and by lowering the impurity concentration of the second region of the barrier layer to about 5×1018 cm-3 as taught by Shin to have the semiconductor device, wherein the first concentration is an order of magnitude or more greater than the second concentration, in order to provide normally-off HEMT having low on-resistance and a high threshold voltage; reduced gate leakage current and stable normally-off characteristics (Miyoshi, Col. 1, lines 9-11; Col. 2, lines 10-50; Col. 4, lines 22-45; Col. 5, lines 9-12; Col. 6, lines 2-4; Shin, ¶0062).
Regarding claim 19, Shin discloses the semiconductor device of claim 18. Further, Shin does not specifically disclose the semiconductor device, wherein the first concentration is greater than the second concentration by an order of magnitude or more.
However, Shin teaches that by lowering the impurity concentration of the second region (e.g., the first barrier layer 31) close to the p-GaN gate layer (40) (Shin, Figs. 6-7, ¶0062), a HEMT device is capable of reducing or preventing a gate leakage current caused by impurity diffusion into the p-type gate layer (40) and has stable normally-off characteristics.
Further, Miyoshi teaches forming a HEMT device (Miyoshi, Figs. 1B, 2A, 4, Col. 1, lines 9-11; Col. 2, lines 10-50; Col. 4, lines 22-45; Col. 5, lines 9-12; Col. 6, lines 2-4) comprising p-type region (5) in the barrier layer (4) immediately under the gate (7) and having an Mg-doping concentration of about 5×1019 cm-3 (Miyoshi, Figs. 1B, 2A, 4, Col. 5, lines 9-12), to provide normally-off HEMT having low on-resistance and a high threshold voltage.
Thus, a person of ordinary skill in the art would recognize that by forming the first region of the barrier layer under the gate having higher Mg-doping concentration of about 5×1019 cm-3 (as taught by Miyoshi), and by lowering the impurity concentration (e.g., to about 5×1018 cm-3) of the second region (e.g., as taught by Shin in Fig. 7), the first concentration would be an order of magnitude or more greater than the second concentration.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming the first region of the barrier layer immediately under the gate having higher Mg-doping concentration of about 5×1019 cm-3 as taught by Miyoshi, and by lowering the impurity concentration of the second region of the barrier layer to about 5×1018 cm-3 as taught by Shin to have the semiconductor device, wherein the first concentration is greater than the second concentration by an order of magnitude or more, in order to provide normally-off HEMT having low on-resistance and a high threshold voltage; reduced gate leakage current and stable normally-off characteristics (Miyoshi, Col. 1, lines 9-11; Col. 2, lines 10-50; Col. 4, lines 22-45; Col. 5, lines 9-12; Col. 6, lines 2-4; Shin, ¶0062).
Claims 8 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0310833 to Shin in view of He et al. (CN 113851522 A, hereinafter He).
Regarding claim 8, Shin discloses the semiconductor device of claim 1. Further, Shin does not specifically disclose the semiconductor device, further comprising: a passivation layer over the gate layer and the barrier layer; and a gate contact over and contacting the gate layer and through the passivation layer.
However, He discloses the semiconductor device, further comprising: a passivation layer (9) (He, Fig. 1, p. 5) over the gate layer (5) and the barrier layer (3/4); and a gate contact (8) over and contacting the gate layer (5) and through the passivation layer (9).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming ta passivation layer over the gate as taught by He to have the semiconductor device, further comprising: a passivation layer over the gate layer and the barrier layer; and a gate contact over and contacting the gate layer and through the passivation layer, in order to provide protection for the HEMT device, and to obtain a high reliability GaN enhancement type power device (He, p.2).
Regarding claim 22, Shin discloses the semiconductor device of claim 1. Further, Shin does not specifically disclose the semiconductor device, further comprising: a passivation layer over the doped GaN gate layer and the AlGaN barrier layer; and a gate contact over and contacting the doped GaN gate layer and through the passivation layer.
However, He discloses the semiconductor device, further comprising: a passivation layer (9) (He, Fig. 1, p. 5) over the doped gate GaN layer (5) and the AlGaN barrier layer (3/4); and a gate contact (8) over and contacting the doped GaN gate layer (5) and through the passivation layer (9).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming ta passivation layer over the gate as taught by He to have the semiconductor device, further comprising: a passivation layer over the doped GaN gate layer and the AlGaN barrier layer; and a gate contact over and contacting the doped GaN gate layer and through the passivation layer, in order to provide protection for the HEMT device, and to obtain a high reliability GaN enhancement type power device (He, p.2).
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 18-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891