DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 2020/0066666) (“Jin”) in view of England et al. (US 9,553,058) (“England”).
With regard to claim 1, fig. 16 of Jin discloses a semiconductor package 1000 comprising: a first die 100; a second die 200 on the first die 100; and a plurality of connection terminals 194a that are between the first die 100 and the second die 200 and are configured to electrically connect 194a the first die 100 to the second die 200, wherein the first die 100 comprises: a first silicon (“silicon”, par [0036]) substrate 102a that has a lower side (bottom of 102a) and an upper side (top of 102a) opposite to the lower side (bottom of 102a); a plurality of first through vias 174a that extend in the first silicon substrate 102a and are electrically connected to the plurality of connection terminals 194a, respectively; a plurality of first chip pads 192a that are on the upper side (top of 102a) of the first silicon substrate 102a and are electrically connected to the first through vias 174a, respectively; and a first dummy pattern (“dummy pattern 197a”, par [0132]) on the upper side (top of 102a) of the first silicon substrate 102a, wherein the second die 200 comprises: a second silicon substrate 102b that has a lower side (bottom of 102b) and an upper side (top of 102b) opposite to the lower side (bottom of 102b), the lower side (bottom of 102b) of the second silicon substrate 102b facing the upper side (top of 102a) of the first silicon substrate 102a; and a plurality of second through vias 174b that extend in the second silicon substrate 102b, wherein the plurality of connection terminals 194a and the plurality of first chip pads 192a are in contact with each other and are electrically connected, respectively, and wherein the first dummy pattern 197a includes a metal film (“metal”, par [0131]) or a polymer film.
Jin does not disclose that the first dummy pattern having a grid shape from a plan view and at least partially surrounding each of the plurality of first chip pads.
However, fig. 1A of England discloses that the first dummy pattern 105 having a grid shape from a plan view and at least partially surrounding each of the plurality of first chip pads 107.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy patterns of Jin in grid pattern as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
With regard to claim 3, Jin does not disclose that the first dummy pattern is in contact with the upper side of the first silicon substrate.
However, fig. 1A of England discloses that the first dummy pattern 105 is in contact with the upper side (top of 101) of the first silicon substrate 101.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin on the through silicon via die as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
With regard to claim 4, fig. 16 of Jin discloses that the first die 100 further comprises a first insulating film 124a that extends along the upper side (top of 102a) of the first silicon substrate 102a.
With regard to claim 6, fig. 16 of Jin discloses that the first dummy pattern 197a is on the first insulating film 124a.
With regard to claim 7, fig. 16 of Jin discloses a thickness of the first dummy pattern 197a in a vertical direction (top to bottom) is greater than a thickness of the first insulating film 124a in the vertical direction (top to bottom).
With regard to claim 8, fig. 16 of Jin does not disclose that the first dummy pattern 197a includes a first sub-pattern (left 197a, fig 16) and a second sub-pattern (right 197a, fig. 16).
Jin does not disclose that the first sub-pattern and the second sub-pattern are not connected to each other.
However, fig. 1C of England discloses that the first sub-pattern 105 and the second sub-pattern 111 are not connected to each other.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
With regard to claim 9, fig. 16 of Jin discloses that the second die 200 further comprises: a plurality of second chip pads 192b that are on the upper side of the second silicon substrate 102b and are electrically connected to the second through vias 174b, respectively, and a second dummy pattern 196b on the upper side of the second silicon substrate 102b.
Jin does not disclose that the second dummy pattern having a grid shape from the plan view and at least partially surrounding each of the plurality of second chip pads.
However, fig. 1A of England discloses that the second dummy pattern 105 having a grid shape from the plan view and at least partially surrounding each of the plurality of second chip pads 107.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
With regard to claim 10, fig. 16 of Jin discloses that the second dummy pattern 196b includes a metal film (“metal”, par [0131]) or a polymer film.
With regard to claim 11, fig. 16 of Jin discloses that a thickness of at least one of the first chip pads 192a in a vertical direction is greater than a thickness of the first dummy pattern 197a in the vertical direction.
Claims 12-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 2020/0066666) (“Jin”), England et al. (US 9,553,058) (“England”), and Park et al. (US 2018/0033779) (“Park”).
With regard to claim 12, figs. 16 and 19 of Jin discloses a semiconductor package comprising: wherein the second semiconductor chip 1000 includes a plurality of dies (100, 200) stacked in a second direction (top to bottom) intersecting the first direction (left to right), and a plurality of connection terminals 194a that are configured to electrically connect the plurality of dies (100, 200) to each other, wherein each of the plurality of dies (100, 200) comprises: a silicon substrate 102a that has a lower side (bottom of 102a) and an upper side (top of 102a) opposite to the lower side (bottom of 102a), the lower side (bottom of 102a) of the silicon substrate 102a facing the interposer structure 600; a plurality of through vias 174a that extend in the silicon substrate 102a and are electrically connected to the plurality of connection terminals 194a, respectively; a plurality of chip pads 192a that are on the upper side (top of 102a) of the silicon substrate 102a and are electrically connected to the through vias 174a, respectively; and an insulating film 124a that extends along the upper side (top of 102a) of the silicon substrate 102a, and wherein at least one of the plurality of dies 100 includes a dummy pattern 197a on the insulating film 124a.
Jin does not disclose a package substrate; an interposer structure on the package substrate; and first and second semiconductor chips on the interposer structure and spaced apart from each other in a first direction, the dummy pattern having a grid shape from a plan view and at least partially surrounding each of the plurality of chip pads of the at least one of the plurality of dies.
However, fig. 1A of England discloses that the dummy pattern 105 having a grid shape from a plan view and at least partially surrounding each of the plurality of chip pads 109 of the at least one of the plurality of dies 101.
England does not disclose a package substrate; an interposer structure on the package substrate; and first and second semiconductor chips on the interposer structure and spaced apart from each other in a first direction.
However, fig. 8 of Park discloses a package substrate 600; an interposer structure 100 on the package substrate 600; and first 400 and second semiconductor chips 200 on the interposer structure 100 and spaced apart from each other in a first direction (left to right).
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
It would have been obvious to one of ordinary skill in the art to form the semiconductor package of Jiin as the chip stack package as taught in Park in order to provide a high bandwidth memory package. See par [0004] of Park.
With regard to claim 13, fig. 16 of Jin does not disclose that the dummy pattern 197a includes a first sub-pattern (left 197a, fig 16) and a second sub-pattern (right 197a, fig. 16).
Jin does not disclose that the first sub-pattern and the second sub-pattern are not connected to each other.
However, fig. 1C of England discloses that the first sub-pattern 105 and the second sub-pattern 111 are not connected to each other.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
With regard to claim 14, fig. 16 of Jin discloses that the first dummy pattern 197a includes a metal film (“metal”, par [0131]) or a polymer film.
With regard to claim 16, fig. 16 of Jin discloses a thickness of the dummy pattern 197a in the second direction (top to bottom) is greater than a thickness of the insulating film 124a in the second direction (top to bottom).
With regard to claim 17, fig. 7 and 16 of Jin discloses a thickness (thickness of 22 and 18 together) of at least one of the chip pads (22, 18) in the second direction is greater than a thickness of the dummy pattern 34 in the second direction (top to bottom in fig. 7).
With regard to claim 18, fig. 16 of Jin discloses the second semiconductor chip 1000 comprises a lower die structure 100 that includes at least one of the plurality of dies 100, and an upper die structure 500 that includes at least one of the plurality of dies 500, the upper die structure 500 is on the lower die structure 100, the at least one of the plurality of dies 100 included in the lower die structure 100 has the dummy pattern 197a, and the at least one of the plurality of dies 500 included in the upper die structure 500 does not have the dummy pattern.
With regard to claim 19, figs. 16 and 19 of Jin discloses a semiconductor package comprising: wherein the memory (“first and second semiconductor chips 100 and 200 may function as memory devices”, par [0141]) chip 1000 includes first 100 and second dies 200 stacked in a second direction (top to bottom) intersecting the first direction (left to right), and a plurality of connection terminals 194a that are configured to electrically connect the first die 100 to the second die 200, wherein the first die 100 comprises: a first silicon substrate 102a that has a lower side (bottom of 102a) and an upper side (top of 102a) opposite to the lower side (bottom of 102a), the lower side (bottom of 102a) of the first silicon substrate 102a facing the interposer structure 600; a plurality of first through vias 174a that extend in the first silicon substrate 102a; a plurality of first chip pads 192a that are on the upper side (top of 102a) of the first silicon substrate 102a and are electrically connected to the first through vias 174a, respectively; a first insulating film 124a that extends along the upper side of the first silicon substrate 102a; and a first dummy pattern 197a on the first insulating film 124a, wherein the second die 200 comprises: a second silicon substrate 102b that has a lower side (bottom of 102b) and an upper side (top of 102b) opposite to the lower side (bottom of 102b), the lower side (bottom of 102b) of the second silicon substrate 102b facing the upper side (top of 102a) of the first silicon substrate 102a; a plurality of second through vias 174b that extend in the second silicon substrate 102b; a plurality of second chip pads 192b that are on the upper side (top of 102b) of the second silicon substrate 102b and are electrically connected to the second through vias 174b, respectively; a second insulating film 124b that extends along the upper side of the second silicon substrate 102b; and a second dummy pattern 196b on the second insulating film 124b, wherein the plurality of connection terminals 194a are in contact with the plurality of first chip pads 192a, respectively, and wherein each of the first 197a and second dummy patterns 196b includes a metal film (“metal”, par [0131]) or a polymer film.
Jin does not disclose a package substrate; an interposer structure on the package substrate; and a logic chip and a memory chip on the interposer structure and spaced apart from each other in a first direction, the first dummy pattern having a grid shape from a plan view and at least partially surrounding each of the plurality of first chip pads, the second dummy pattern having a grid shape from the plan view and at least partially surrounding each of the plurality of second chip pads.
However, fig. 1A of England discloses the first dummy pattern 105 having a grid shape from a plan view and at least partially surrounding each of the plurality of first chip pads 107, the second dummy pattern (105 in another TSV die of a 3D IC stack, col. 2 ll. 25) having a grid shape from the plan view and at least partially surrounding each of the plurality of second chip pads (107 in another SV die of the 3D IC stack, col. 2 ll. 25).
England does not disclose a package substrate; an interposer structure on the package substrate; and a logic chip and a memory chip on the interposer structure and spaced apart from each other in a first direction.
However, fig. 8 of Park discloses a package substrate 600; an interposer structure 100 on the package substrate 600; and a logic (“CPU”, par [0052]) chip 400 and a memory (“memory”, par [0050]) chip 200 on the interposer structure 100 and spaced apart from each other in a first direction (left to right).
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
It would have been obvious to one of ordinary skill in the art to form the semiconductor package of Jiin as the chip stack package as taught in Park in order to provide a high bandwidth memory package. See par [0004] of Park.
With regard to claim 20, fig. 16 of Jin does not disclose that the first dummy pattern 197a includes a first sub-pattern (left 197a, fig 16) and a second sub-pattern (right 197a, fig. 16).
Jin does not disclose that the first sub-pattern and the second sub-pattern are not connected to each other.
However, fig. 1C of England discloses that the first sub-pattern 105 and the second sub-pattern 111 are not connected to each other.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy pattern of Jin with the RDL lines as taught in England in order to provide custom levels of warpage compensation. See col. 3 ll. 58 of England.
Allowable Subject Matter
Claims 2, 5, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893