DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
[0029] Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. In an embodiment, the storage system compensates for physical differences between different memory cells undergoing erase. For example, some NAND strings may erase more slowly than others. Therefore, it is possible that some NAND strings may pass erase while others need more erase loops to pass. In some cases, erase of the slower NAND strings is so slow that it will take multiple additional loops to pass erase. These extra erase loops could damage memory cells on the faster to erase NAND strings. The storage system prevents damage to memory cells on the faster to erase NAND strings while allowing enough erase loops to complete erase of the slower to erase NAND strings. The term “erase saturation” may be used to refer to a slow to erase NAND string that doesn’t respond much to the erase pulse.
[0030] In one embodiment, the storage system will perform a number of erase loops in which each loop an erase pulse is applied to memory cells on a group of NAND strings and an erase verify is performed. If erase does not pass after a number of erase loops the storage system applies a program pulse to memory cells on the faster to erase NAND strings, such as the NAND strings that passed erase. However, memory cells on the slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. At this point the erase process could end. However, the process could continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.
[0099] Step 602 includes setting an initial magnitude of an erase voltage (Vera). The initial Vera may have a relatively large magnitude such as, for example, 20V. Step 602 also includes setting a loop counter to 0. The loop counter will be used to track an allowed number of erase loops prior to ending process 600 in the event erase has not passed. Step 604 includes applying Vera to bit lines associated with the erase group. Step 606 includes applying Vera to one or more source lines associated with the erase group. Step 608 includes applying an erase enable voltage to the word lines in the erase block. In one embodiment, the erase enable voltage is 0V but could be other than 0V such as about 0.5V. Step 610 includes applying a select voltage (turn-on voltage) to select lines (e.g., SGD, SGS). The select voltage allows Vera to pass to the NAND channels.
[00104] In an embodiment, the erase saturation mitigation includes applying a programming voltage to memory cells that passed the erase while inhibiting programming to memory cells that did not pass the erase. Then, an additional erase voltage may be applied to the erase group. More specifically, steps 604 – 612 may be performed again. If erase has still not passed, then the storage system 100 may perform the additional actions just described to continue on with the erase until erase has been completed. There may be another loop counter to limit how many times these additional actions are performed.
[00106] Figure 7A shows an example Vt distribution after a number of erase loops. As an example, process 600 may have been performed to the point at which step 618 resulted in a conclusion that erase saturation mitigation should be performed. The erase verify reference of Vev is used to determine whether a NAND string passes erase. The term Vt of a NAND string may be used herein to refer to the highest Vt of a memory cell being erased on the NAND string, as that may be the determining factor in whether the NAND string passes erase. Vt distribution 710 shows that a large number of NAND strings have a Vt below Vev and therefore passed erase. However, a significant number of NAND strings have a Vt above Vev and therefore did not pass erase. The Vt of the slower to erase NAND strings might not drop very much in response to an additional erase pulse (even if higher in magnitude than the previous erase pulse). For example, an additional erase pulse that is 0.4V higher than the previous erase pulse might only drop the Vt of a slow to erase NAND string by about 0.1V. The term “erase saturation” may be used to refer to a slow to erase NAND string that doesn’t respond much to the erase pulse.
[00128] Figure 11 is a flowchart of one embodiment of a process 1100 of flash programming memory cells on NAND strings. Flash programming, as the term is defined herein, means to increase the Vt of more than one memory cell on a NAND string simultaneously. The Vts of the memory cells may be increased by applying a program pulse to the control gates of memory cells while applying a program enable voltage to the bit line(s) connected to the NAND string(s). Process 1100 is one technique for selective increasing the Vt of memory cells that may be used in step 810 of process 800.
Appropriate correction is required.
Drawings
The drawings are objected to because of the following:
Regarding Figure 6: It is suggested to change 602 to “Set initial magnitude of Vera and set Loop Count to 0”. It is suggested to change 610 to “Apply turn-on voltages to select lines” or “Apply select voltages to select lines”.
Regarding Figure 8: It is suggested to change 808 to “Identify memory cells or NAND strings that are slow to erase and those that are not slow to erase” (see [0117]).
Regarding Figure 11: It is suggested to change 1114 to “apply program voltage to selected word lines simultaneously” (see [0128]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9, 10, and 18-20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9: It is noted that Applicant provided a definition of “flash programming” in [0128] of the specification by stating “Flash programming, as the term is defined herein, means to increase the Vt of more than one memory cell on a NAND string simultaneously.”. The phrase “flash program” is used in claim 10; however, since this term does not exactly match the term “flash programming”, then it is indefinite as to whether Applicant intended the limitation “to increase the Vt of more than one memory cell on a NAND string simultaneously” to be read into the claim limitations.
If Applicant intends to incorporate the said limitation of the [0128] into the claim then Examiner suggests amending the claim as follows:
The apparatus of claim 8, wherein to selectively increase the threshold voltages of the first set of the memory cells the one or more control circuits are configured to perform the following for at least two sets of the group of the word lines:
select a set of word lines connected to the NAND strings; and
flash program the set of the word lines simultaneously while inhibiting program of other word lines connected to the NAND strings.
Regarding claim 10: It is noted that Applicant provided a definition of “flash programming” in [0128] of the specification by stating “Flash programming, as the term is defined herein, means to increase the Vt of more than one memory cell on a NAND string simultaneously.”. The phrase “flash program” is used in claim 10; however, since this term does not exactly match the term “flash programming”, then it is indefinite as to whether Applicant intended the limitation “to increase the Vt of more than one memory cell on a NAND string simultaneously” to be read into the claim limitations.
If Applicant intends to incorporate the said limitation of the [0128] into the claim then Examiner suggests amending the claim as follows:
The apparatus of claim 1, wherein:
the memory structure comprising blocks, each block comprising a plurality of word lines and a plurality of NAND strings, each word line in a block connected to each NAND string in the block, each block comprising a plurality of select lines configured to select a different sub-block in the block, the memory structure having a plurality of bit lines, each NAND string associated with a bit line; and
to selectively increase the threshold voltages of the first set of the memory cells the one or more control circuits are configured to perform the following:
apply a voltage to one of the select lines to select a sub-block in a selected block; and
flash program selected NAND strings in the selected sub-block, wherein the threshold voltages of more than one memory cell of each of the selected NAND strings are simultaneously increased, while inhibiting programming of unselected NAND strings in the selected sub-block and while inhibiting programming of NAND strings in un-selected sub-blocks of the selected block.
Regarding claim 18: It is noted that Applicant provided a definition of “flash programming” in [0128] of the specification by stating “Flash programming, as the term is defined herein, means to increase the Vt of more than one memory cell on a NAND string simultaneously.”. The phrase “flash program” is used in claim 10; however, since this term does not exactly match the term “flash programming”, then it is indefinite as to whether Applicant intended the limitation “to increase the Vt of more than one memory cell on a NAND string simultaneously” to be read into the claim limitations.
If Applicant intends to incorporate the said limitation of the [0128] into the claim then Examiner suggests amending the claim as follows:
The non-volatile storage system of claim 16, wherein to program the first memory cells while inhibiting from programming all other memory cells in the selected block the one or more control circuits are further configured to:
flash program selected NAND strings in a selected sub-block in the selected block such that the threshold voltages of more than one memory cell of a NAND string are simultaneously increased;
inhibit programming of unselected NAND strings in the selected sub-block; and
inhibit programming of NAND strings in unselected sub-block of the selected block.
Regarding claim 19: It is noted that Applicant provided a definition of “flash programming” in [0128] of the specification by stating “Flash programming, as the term is defined herein, means to increase the Vt of more than one memory cell on a NAND string simultaneously.”. The phrase “flash program” is used in claim 10; however, since this term does not exactly match the term “flash programming”, then it is indefinite as to whether Applicant intended the limitation “to increase the Vt of more than one memory cell on a NAND string simultaneously” to be read into the claim limitations. Claim 20 depends on claim 19.
If Applicant intends to incorporate the said limitation of the [0128] into the claim then Examiner suggests amending the claim as follows:
The non-volatile storage system of claim 16, wherein to program the first memory cells while inhibiting from programming all other memory cells in the selected block the one or more control circuits are further configured to:
i) flash program a set of selected word lines simultaneously in the selected block;
ii) inhibit programming of unselected word lines in the selected block; and
iii) repeat said i) and said ii) for one or more sets of selected word lines in the selected block
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fastow et al. (US 6,438,037).
Rejected claim 1: Fastow (FIG. 1; lines 1-58 of column 5; claims 8-10; FIG. 6) teaches an apparatus comprising:
one or more control circuits (114 in FIG. 1) configured to connect to a memory structure comprising non-volatile memory cells (memory transistors 101), the one or more control circuits configured to:
apply erase conditions to a group of the memory cells one or more times (First Erase Operation in step 602 in FIG. 6 such that memory cells are in an erased distribution state 300 shown in FIG. 3);
divide the group of the memory cells into a first set of the memory cells (memory cells in FIG. 3 having a threshold voltage less than Vm) that were faster to erase and a second set of the memory cells (memory cells in FIG. 3 having a threshold voltage greater than Vm) that were slower to erase after applying the erase conditions the one or more times (Read-Verify Operation step 604 identifies which cells of distribution 300 are fast erase memory cells and which cells are slow erase memory cells);
selectively increase threshold voltages of the first set of the memory cells (Soft-Program Operation step 606); and
apply additional erase conditions to the group of the memory cells after selectively increasing the threshold voltages of the first set of the memory cells (Second Erase Operation 608 of FIG. 6).
Regarding claim 2: Fastow teaches the apparatus of claim 1, wherein the one or more control circuits are further configured to:
verify erase of the group of memory cells after applying the additional erase conditions to the group of the memory cells (lines 54-65 of column 8 and liens 1-8 of column 9); and
provide a status of erase pass for the group of memory cells responsive to the group of memory cells passing erase (“setting the Vt for the memory cells to a value less than a second erase-verify voltage Vev2”; cells are verified to have a Vt less than Vev2 and/or above Vs2; see FIG. 5) after applying the additional erase conditions (lines 54-65 of column 8 and liens 1-8 of column 9).
Regarding claim 3: Fastow (lines 54-65 of column 8) teaches the apparatus, wherein responsive to the group of memory cells not passing erase after applying the additional erase conditions the one or more control circuits are further configured to perform the following one or more times until the group passes erase:
identify a present set of the memory cells that passed erase and a present set of the memory cells that do not pass the erase after a most recent set of erase conditions were applied (see “memory cells verified as having a Vt less than a second selected reference voltage” are identified);
selectively increase threshold voltages of the present set of the memory cells that passed erase after the most recent set of erase conditions were applied (606 is repeated); and
apply another set of erase conditions to the group of the memory cells after selectively increasing the threshold voltages of the present set of the memory cells that passed erase (608 is repeated since it happens after 606).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 4, 6, 8, 10 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 6,438,037) in view of Choi et al. (US 2003/0133679).
Regarding claim 4: Fastow does not specifically teach the one or more control circuits are further configured to:
program the first set of the memory cells while inhibiting programming of the second set of the memory cells to selectively increase the threshold voltage of the first set of the memory cells.
Choi teaches a NAND memory structure (FIG. 4), wherein fast erase memory cells are addressed in a fashion similar to that taught by Fastow (FIG. 10, FIG. 11), the NAND memory structure comprising a selected block comprising a plurality of NAND strings, each word line in the block connected to each NAND string in the block, and each NAND string associated with a bit line BL; and first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block (inherently the fast erase cells in region A in FIG. 3 or FIG. 13A are in NAND strings of the selected block and the non-fast erase cells or slower erase cells NOT in A are in NAND strings of the selected block). Furthermore, Choi ([0013]; FIG. 2A) teaches programming selected memory cells while inhibiting programming of other memory cells to selectively increase the threshold voltage of the selected memory cells.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Choi into the device and/or method of Fastow in a manner such that the memory flash memory array would comprise a plurality of NAND blocks, each block comprising a plurality of NAND strings, each word line in a block connected to each NAND string in the block, and each NAND string associated with a bit line;
the first memory cells would be on a first set of NAND strings and the second memory cells would be on a second set of NAND strings in a selected block; and
the first set of the memory cells would be programmed while inhibiting programming of the second set of the memory cells to selectively increase the threshold voltage of the first set of the memory cells.
The motivation to do so would have been to apply the teachings of Fastow to a NAND type flash memory structure instead of the flash memory structure of Fastow, which is recognized as a NOR type flash memory structure, to address the same problem of fast-to-erase or over-erased memory cells that also exists in NAND type flash memory as evidenced by Choi.
Regarding claim 6: Fastow does not specifically teach selectively increasing the threshold voltage of first set of the memory cells comprises the one or more control circuits: applying a program pulse to control gates of the group of the memory cells; applying a program enable voltage to bit lines connected to NAND strings that have the first set of the memory cells; and applying a program inhibit voltage to bit lines connected to NAND strings that have the second set of the memory cells.
Choi teaches a NAND memory structure (FIG. 4), wherein fast erase memory cells are addressed in a fashion similar to that taught by Fastow (FIG. 10, FIG. 11), the NAND memory structure comprising a selected block comprising a plurality of NAND strings, each word line in the block connected to each NAND string in the block, and each NAND string associated with a bit line BL; and first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block (inherently the fast erase cells in region A in FIG. 3 or FIG. 13A are in NAND strings of the selected block and the non-fast erase cells or slower erase cells NOT in A are in NAND strings of the selected block). Furthermore, Choi ([0012-0014]; FIG. 2A) teaches applying a program pulse (Vpgm in FIG. 2A) to control gates of the group of the memory cells; applying a program enable voltage to bit lines connected to NAND strings that have the first set of the memory cells (a voltage corresponding to a logic value of “0”); and applying a program inhibit voltage to bit lines connected to NAND strings that have the second set of the memory cells (a voltage corresponding to a logic value of “1”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Choi into the device and/or method of Fastow in a manner such that the memory flash memory array would comprise a plurality of NAND blocks, each block comprising a plurality of NAND strings, each word line in a block connected to each NAND string in the block, and each NAND string associated with a bit line;
the first memory cells would be on a first set of NAND strings and the second memory cells would be on a second set of NAND strings in a selected block; and
selectively increasing the threshold voltage of first set of the memory cells comprises the one or more control circuits: applying a program pulse to control gates of the group of the memory cells; applying a program enable voltage to bit lines connected to NAND strings that have the first set of the memory cells; and applying a program inhibit voltage to bit lines connected to NAND strings that have the second set of the memory cells.
The motivation to do so would have been to apply the teachings of Fastow to a NAND type flash memory structure instead of the flash memory structure of Fastow, which is recognized as a NOR type flash memory structure, to address the same problem of fast-to-erase or over-erased memory cells that also exists in NAND type flash memory as evidenced by Choi.
Regarding claim 8: Fastow does not specifically teach the group of the memory cells reside on a group of NAND strings; and the memory structure comprises a group of word lines with each word line connecting to each NAND string in the group
Choi teaches a NAND memory structure (FIG. 4), wherein fast erase memory cells are addressed in a fashion similar to that taught by Fastow (FIG. 10, FIG. 11), the NAND memory structure comprising a selected block comprising a plurality of NAND strings, each word line in the block connected to each NAND string in the block, and each NAND string associated with a bit line BL; and first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block (inherently the fast erase cells in region A in FIG. 3 or FIG. 13A are in NAND strings of the selected block and the non-fast erase cells or slower erase cells NOT in A are in NAND strings of the selected block). Furthermore, Choi ([0013]; FIG. 2A) teaches programming selected memory cells while inhibiting programming of other memory cells to selectively increase the threshold voltage of the selected memory cells.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Choi into the device and/or method of Fastow in a manner such that the memory flash memory array would comprise a plurality of NAND blocks, each block comprising a plurality of NAND strings, each word line in a block connected to each NAND string in the block, and each NAND string associated with a bit line; and
the first memory cells would be on a first set of NAND strings and the second memory cells would be on a second set of NAND strings in a selected block.
The motivation to do so would have been to apply the teachings of Fastow to a NAND type flash memory structure instead of the flash memory structure of Fastow, which is recognized as a NOR type flash memory structure, to address the same problem of fast-to-erase or over-erased memory cells that also exists in NAND type flash memory as evidenced by Choi.
Regarding claim 10: In so far as definite, Fastow does not specifically teach the following:
the memory structure comprising blocks, each block comprising a plurality of word lines and a plurality of NAND strings, each word line in a block connected to each NAND string in the block, each block comprising a plurality of select lines configured to select a different sub-block in the block, the memory structure having a plurality of bit lines, each NAND string associated with a bit line; and
to selectively increase the threshold voltages of the first set of the memory cells the one or more control circuits are configured to perform the following: apply a voltage to one of the select lines to select a sub-block in a selected block; and flash program selected NAND strings in the selected sub-block while inhibiting programming of unselected NAND strings in the selected sub-block and while inhibiting programming of NAND strings in un-selected sub-blocks of the selected block.
Choi teaches a NAND memory structure (FIG. 4), wherein fast erase memory cells are addressed in a fashion similar to that taught by Fastow (FIG. 10, FIG. 11), the NAND memory structure comprising a selected block comprising a plurality of NAND strings, each word line in the block connected to each NAND string in the block, and each NAND string associated with a bit line BL; and first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block (inherently the fast erase cells in region A in FIG. 3 or FIG. 13A are in NAND strings of the selected block and the non-fast erase cells or slower erase cells NOT in A are in NAND strings of the selected block). Furthermore, Choi (TABLE 2) teaches voltage biases applied to a selected block and an unselected block during a program operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Choi into the device and/or method of Fastow in a manner such that:
the memory structure would comprise blocks, each block comprising a plurality of word lines and a plurality of NAND strings, each word line in a block connected to each NAND string in the block, each block comprising a plurality of select lines configured to select a different sub-block in the block, the memory structure having a plurality of bit lines, each NAND string associated with a bit line (like the NAND structure of Choi); and
the threshold voltages of the first set of the memory cells would be selectively increased by the one or more control circuits being configured to perform the following: apply a voltage to one of the select lines to select a sub-block in a selected block; and flash program selected NAND strings in the selected sub-block while inhibiting programming of unselected NAND strings in the selected sub-block and while inhibiting programming of NAND strings in un-selected sub-blocks of the selected block like that taught by TABLE 2 of Choi (note that the programming of one memory cell on each stinrg of a plurality of selected NAND strings is being interpreted to read on “flash program selected NAND strings”).
The motivation to do so would have been to apply the teachings of Fastow to a NAND type flash memory structure instead of the flash memory structure of Fastow, which is recognized as a NOR type flash memory structure, to address the same problem of fast-to-erase or over-erased memory cells that also exists in NAND type flash memory as evidenced by Choi.
Regarding claim 16: Fastow (FIG. 1; lines 1-58 of column 5; claims 8-10; FIG. 6) teaches a non-volatile storage system comprising:
a memory structure comprising blocks, each block (flash memory array 100) comprising a plurality of word lines (109), each word line in a block connected to a row of flash memory cells (101), the memory structure having a plurality of bit lines (104), each flash memory cell associated with a bit line [of the bit lines]; and
one or more control circuits (114) in communication with the memory structure, wherein the one or more control circuits are configured to:
apply a plurality of erase voltages to a group of memory cells in a selected block, the group of memory cells connected to a set of the word lines in the selected block (First Erase Operation 602 in FIG. 6); and
responsive to a determination that first memory cells in the selected block passed erase (fast erase memory cells identified in step 604) and second memory cells on a second set of NAND strings in the selected block did not pass the erase (the memory cells not identified as fast erase memory cells in step 604) after applying the plurality of erase voltages (after 602):
program the first memory cells while inhibiting from programming all other memory cells in the selected block (Soft-Program Operation 606); and
apply an additional erase voltage to the group of memory cells in the selected block after programming the first memory cells (Second Erase Operation 608).
Fastow does not specifically teach the following:
each block comprising a plurality of NAND strings, each word line in a block connected to each NAND string in the block, and each NAND string associated with a bit line; and
the first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block.
Choi teaches a NAND memory structure (FIG. 4), wherein fast erase memory cells are addressed in a fashion similar to that taught by Fastow (FIG. 10, FIG. 11), the NAND memory structure comprising a selected block comprising a plurality of NAND strings, each word line in the block connected to each NAND string in the block, and each NAND string associated with a bit line BL; and first memory cells are on a first set of NAND strings and the second memory cells are on a second set of NAND strings in the selected block (inherently the fast erase cells in region A in FIG. 3 or FIG. 13A are in NAND strings of the selected block and the non-fast erase cells or slower erase cells NOT in A are in NAND strings of the selected block).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Choi into the device and/or method of Fastow in a manner such that the memory flash memory array would comprise a plurality of NAND blocks, each block comprising a plurality of NAND strings, each word line in a block connected to each NAND string in the block, and each NAND string associated with a bit line; and
the first memory cells would be on a first set of NAND strings and the second memory cells would be on a second set of NAND strings in a selected block. The motivation to do so would have been to apply the teachings of Fastow to a NAND type flash memory structure instead of the flash memory structure of Fastow, which is recognized as a NOR type flash memory structure, to address the same problem of fast-to-erase or over-erased memory cells that also exists in NAND type flash memory as evidenced by Choi.
Regarding claim 17: Fastow (lines 54-65 of column 8) teaches the non-volatile storage system of claim 16, wherein the one or more control circuits are further configured to:
verify whether both the first memory cells and the second memory cells are erased after the additional erase voltage is applied to the group of memory cells (verifying using Vev2 so as to verify that all cells have a Vt less than Vev2; see FIG. 5);
report a status of erase passed for the group of memory cells in the selected block responsive to a determination that both the first memory cells and the second memory cells are erased after the additional erase voltage is applied (if all memory cells in the selected block have Vt between Vs2 and Vev2 then erase is passed); and
perform the following until the group of memory cells are erased responsive to a determination that the group of memory cells are not erased (some cells being over erased if they have a Vt less than Vs2) after the additional erase voltage is applied:
program memory cells that passed erase (have a Vt lower than Vev2 but lower than Vs2; fast cells or over erased cells) after the most recent additional erase voltage is applied while inhibiting from programming memory cells all other memory cells in the selected block (soft-program operation 606 is repeated on such cells); and
apply an additional erase voltage to the group of memory cells in the selected block (step 608 is after 606 in FIG. 6 so it too is repeated until the cells are in the Vt range between Vs2 and Vev2 as illustrated in FIG. 5).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 6,438,037) in view of Chun et al. (US 20100118613).
Regarding claim 7: Fastow (FIG. 3) teaches memory cells having a threshold voltage less than an erase verify voltage (Vm) are placed into the first set, and memory cells having a threshold greater than the erase verify voltage are placed into the second set (see read-verify operation 604 in FIG. 6; lines 17-53 of column 8).
Fastow does not specifically teach the one or more control circuits are further configured to apply an erase verify voltage to control gates of the group of the memory cells to identify the first set and the second set of the memory cells.
Chun ([0007, 0088]) states “In the detecting of the flash memory cell whose threshold voltage is less than the first voltage, the first voltage may be applied to a word line connected to a gate of the at least one flash memory cell, and then it may be determined whether the threshold voltage of the flash memory cell is less than the first voltage based on whether a current flows through the flash memory cell.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chun into the device and/or method of Fastow in a manner such that the one or more control circuits would be further configured to apply an erase verify voltage to control gates of the group of the memory cells to identify the first set and the second set of the memory cells. The motivation to do so would have been to perform a voltage to the word line such that the fast erase cells and the slow erase cells (the non-fast erase cells) would be identified so that it would be known on which cells to execute the soft-program operation 606 of Fastow (see FIG. 6 of Fastow).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al. (US 6,438,037) in view of Lee et al. (20050086413).
Regarding claim 11: Fastow does not specifically teach the apparatus of claim 1, wherein the apparatus further comprises:
a first semiconductor die that comprises the memory structure; and
a second semiconductor die that comprises the one or more control circuits.
Lee (FIG. 3A; [0022]) teaches a flash-memory drive comprising a flash memory chip 13 being controlled by a flash memory controller chip 12.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lee into the device and/or method of Fastow in a manner such that at least a portion of the control circuitry of Fastow (114 in FIG. 1) would be located on a separate die like that taught by Lee (see controller chip 12 in FIG. 3A of Lee) and the flash memory array would be located on another die like that taught by Lee (see flash memory chip 13 in FIG. 3A of Lee). The motivation to do so would have been to realize a flash memory drive like that disclosed by Lee.
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the control circuits are further configured to apply different program pulses to different subsets of the memory cells in the first set when programming the first set of the memory cells; and establish a magnitude for the different program pulses based on location of the subsets of the memory cells in combination with the other limitations thereof as is recited in the claim.
Regarding claim 12: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of programming the selected memory cells on the selected NAND strings that passed erase while inhibiting from programming the selected memory cells on the selected NAND strings that did not pass erase after applying the plurality of erase pulses; and applying an additional erase pulse to the selected NAND strings after programming the selected memory cells on the selected NAND strings that passed erase in combination with the other limitations thereof as is recited in the claim. Claims 13-15 depend on claim 12.
Conclusion
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827