DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restrictions
Applicant's election with traverse of Species A in the reply filed on 10/20/2025 is acknowledged. The traversal is on the ground(s) that the search and examination of all the claims may be made without serious burden. The Requirement for Restriction has been withdrawn.
Claim Objections
Claims 1 and 20 are objected to because of the following informalities: The mentioning of “high voltage” or “low voltage” is a broad term and does not indicate any clear differences as the terms are relative.
As to claim 7, the recitation of “immediately adjacent” appears incorrect in regards to the first high voltage line and first low voltage line due to them being “separated from each other”. Appropriate correction is required.
As to claim 11, the recitation of “immediately adjacent” appears incorrect in regards to the second high voltage line and the second low voltage line due to them being “separated from each other”. Appropriate correction is required.
IDS
The IDS document(s) filed on 07/27/2023 and 05/28/224 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 11, 13-15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0217765 A1), hereafter “Kim”.
As to claim 1, Kim teaches a semiconductor memory device comprising:
a peripheral region (Fig. 4A, PS, ⁋ [0027]) including
a lower substrate (SUB, ⁋ [0031]),
high voltage transistors (PTR, ⁋ [0036]) on the lower substrate,
first lower lines (INL1+INLD1, ⁋⁋ [0038], [0041]) electrically connected to the high voltage transistors (⁋ [0038]), and
second lower lines (INL3+INLD3, ⁋⁋ [0038], [0041]) electrically connected to the first lower lines over the first lower lines; and
a cell region (CS, ⁋ [0027]) on the peripheral region,
the first lower lines and the second lower lines extending along a first direction (D2, Fig. 4A) parallel to an upper surface of the lower substrate,
the first lower lines including first high voltage lines (INL1) and first low voltage lines (INLD1),
the second lower lines including second high voltage lines (INL3) and second low voltage lines (INLD3),
the second high voltage lines (INL3) and the first low voltage lines (INLD1) being separated in a second direction (D2) parallel to the upper surface of the lower substrate and a third direction (D3) perpendicular to the upper surface of the lower substrate (Fig. 4A), and
the second low voltage lines (INLD3) and the first high voltage lines (INL1) being separated in the second direction and the third direction (Fig. 4A).
As to claim 2, Kim teaches the semiconductor memory device of claim 1, wherein the first high voltage lines face each of the second high voltage lines along the third direction (Fig. 4A shows INL1 facing INL3 along D3).
As to claim 3, Kim teaches the semiconductor memory device of claim 1, wherein the first low voltage lines face each of the second low voltage lines along the third direction (Fig. 4A shows INLd1 facing INLd3 along D3).
As to claim 4, Kim teaches the semiconductor memory device of claim 1, wherein a gap between the first lower lines and the second lower lines is smaller than a gap between the first lower lines and a gap between the second lower lines (Fig. 4A shows the gap between INL1 and INL3, and the gap between INLd1 and INLd3 are smaller than the gap between INL1 and INLd3, as well as INL3 and INLd3).
As to claim 5, Kim teaches the semiconductor memory device of claim 1, wherein the first lower lines further include first dummy lines between the first high voltage lines and the first low voltage lines (first low voltage lines INLd1 are dummy lines).
As to claim 7, Kim teaches the semiconductor memory device of claim 5, wherein a first high voltage line and a first low voltage line immediately adjacent to each other among the first high voltage lines and the first low voltage lines are separated from each other with at least one of the first dummy lines interposed therebetween (first low voltage lines INLd1 are dummy lines, also see objection above).
As to claim 8, Kim teaches the semiconductor memory device of claim 5, wherein a gap between the first lower lines and the second lower lines is smaller than a gap between the first lower lines (see claim 4).
As to claim 9, Kim teaches the semiconductor memory device of claim 1, wherein the second lower lines further include second dummy lines between the second high voltage lines and the second low voltage lines (second low voltage lines INLd3 are dummy lines).
As to claim 11, Kim teaches the semiconductor memory device of claim 9, wherein a second high voltage line and a second low voltage line immediately adjacent to each other among the second high voltage lines and the second low voltage lines are separated from each other with at least one of the second dummy lines interposed therebetween (second low voltage lines INLd3 are dummy lines, also see objection above).
As to claim 13, Kim teaches the semiconductor memory device of claim 1, wherein the peripheral region (PS) further includes middle lines (INL2+INLd2, ⁋⁋ [0038], [0041]) electrically connected to the second lower lines (INL3+INLd3), and the middle lines extend along the second direction (D2) on the second lower lines.
As to claim 14, Kim teaches the semiconductor memory device of claim 13, wherein the peripheral region further includes upper lines electrically (Vid3, ⁋ [0042]) connected to the middle lines, and wherein the upper lines extend along the first direction (D2) on the middle lines.
As to claim 15, Kim teaches the semiconductor memory device of claim 14, wherein the cell region further includes: a cell array comprising a gate stack (⁋ [0069], “The electrodes EL of the electrode structure ST may be used as gate electrodes of transistors”) and vertical channels (VS, ⁋ [0061]) and vertical channels (VS, ⁋ [0061]) penetrating the gate stack along the third direction (D3); and bit lines (Fig. 4B, BL, ⁋ [0074]) extending along the first direction (D1) on the cell array, the bit lines electrically connected to the vertical channels (⁋ [0074], “Each of the bit lines BL may be electrically connected to the vertical semiconductor pattern SP through the bit line contact plug BPLG”) and the upper lines (⁋ [0076]).
As to claim 19, Kim teaches the semiconductor memory device of claim 1, wherein the first high voltage lines (INL1), the second high voltage lines, the first low voltage lines, or the second low voltage lines are arranged to be immediately adjacent to each other along the second direction (D2) (Fig. 4A shows INL1 to be immediately adjacent in the D2 direction with nothing directly between).
As to claim 20, Kim teaches a semiconductor memory device comprising:
a lower substrate (Fig. 4B, SUB, ⁋ [0031]);
high voltage transistors (PTR, ⁋ [0036]) on the lower substrate;
first high voltage lines electrically connected to a high voltage source/drain region of the high voltage transistors (see annotated Fig. 4B);
second high voltage lines electrically connected to the first high voltage lines on the first high voltage lines (see annotated Fig. 4B);
first low voltage lines electrically connected to a low voltage source/drain region of the high voltage transistors (see annotated Fig. 4B);
second low voltage lines electrically connected to the first low voltage lines on the first low voltage lines (see annotated Fig. 4B);
a cell array (CS, ⁋ [0027]) on the second low voltage lines and including a gate stack (⁋ [0069], “The electrodes EL of the electrode structure ST may be used as gate electrodes of transistors”) and vertical channels (VS, ⁋ [0061]) penetrating the gate stack along a vertical direction; and
bit lines (Fig. 4B, BL, ⁋ [0074]) electrically connected to the vertical channels (VS) (⁋ [0074], “Each of the bit lines BL may be electrically connected to the vertical semiconductor pattern SP through the bit line contact plug BPLG”) and the second high voltage lines (⁋ [0076]),
the first high voltage lines, the second high voltage lines, the first low voltage lines, the second low voltage lines, and the bit lines extending along a first direction parallel (D1) to an upper surface of the lower substrate.
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Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim.
As to claim 12, Kim fails to teach, wherein a gap between the first lower lines and the second lower lines is greater than a gap between the second lower lines. Kim teaches the gap between the first lower lines and the second lower lines are smaller than a gap between the second lower lines (see claim 4).
On the other hand, Examiner notes the Applicant has not specified a criticality to the dimensions.
If the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Lee et al. (US 2022/0085048 A1), hereafter “Lee”.
As to claim 17, Kim fails to teach the semiconductor memory device of claim 1, wherein the peripheral region further includes low voltage transistors on the lower substrate, and the high voltage transistors and the low voltage transistors are separated from each other along the first direction.
Lee teaches a similar memory device with a peripheral region (PCS, Fig. 2, ⁋ [0044]) contains a high voltage and low voltage transistors separated from each other (⁋ [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the high-voltage and low-voltage transistors as taught by Lee into the semiconductor device of Kim since this configuration would’ve already been known in the art to be used in a peripheral region.
Indication of Allowable Subject Matter
Claims 6, 10, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 6, Kim is the closest prior art and fails to teach wherein a first group of the second high voltage lines face each of the first high voltage lines along the third direction, and a second group of the second high voltage lines face each of the first dummy lines along the third direction.
As to claim 10, Kim is the closest prior art and fails to teach wherein a first group of the first low voltage lines face each of the second low voltage lines along the third direction, and a second group of the first low voltage lines face each of the second dummy lines along the third direction.
As to claim 16, Kim is the closest prior art and fails to teach wherein each of the high voltage transistors includes a high voltage source/drain region and a low voltage source/drain region, and the first high voltage lines are electrically connected to the high voltage source/drain region of the high voltage transistors.
As to claim 18, Kim is the closest prior art and fails to teach wherein each of the high voltage transistors includes a high voltage source/drain region and a low voltage source/drain region, and the first low voltage lines and the second low voltage lines are electrically connected to the low voltage source/drain region of the high voltage transistors and one of a pair of source/drain regions of the low voltage transistors.
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893