Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14, in the reply filed on 11/26/2025 is acknowledged.
Claim Objections
Claim 10 is objected to because of the following informalities: The underlined word in the sentence of ‘N is a second integer grater than 1’ should be corrected as ‘greater’. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (US-20220045089-A1 referred as Mizutani) in view of Ishii et al. (US-20190319040-A1 referred as Ishii).
Regarding claim 1. Mizutani discloses a memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers ([0145], figure 18b, an alternating stack of insulating layers #32 and electrically conductive layers #46 is illustrated);
memory openings vertically extending through the alternating stack ([0145, 0090], figure 18b and figure 3b, the memory openings #49 vertically extend through the alternating stack (#32, #42). Please note the alternating stack (#32, #42) is later updated to the alternating stack (#32, #46) with the electrically conductive layer #46 in place);
memory opening fill structures located in the memory openings and comprising a respective memory film and a respective vertical semiconductor channel ([0113], figure 18b, the memory opening fill structures #58 are located in the memory openings #49 which contains a respective memory film #50 and a respective vertical semiconductor channel #60);
a single contact well vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers ([0121], figure 10b, the contact well #269 vertically extends through the alternating stack (#32, #42) including the topmost insulating layer #32. Please note the alternating stack (#32, #42) containing the sacrificial layer #42 is later replaced with the electrically conductive layers #46 which is seen in its final form of figure 18b);
dielectric fill structures located in the contact well ([0145], figure 18b, the dielectric fill structure #165 is seen located in the contact well #269); and
an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers comprising a plurality of electrically conductive layers that are vertically spaced apart ([0145], figure 18b, an array of contact via structures #286 is seen vertically extending through the respective dielectric fill structure #165 in each of the contact well #269 and contacting a top surface of a respective electrically conductive layer #46 which is within a subnet of electrically conductive layers #46 also spaced apart).
Mizutani lacks having multiple contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers
Ishii discloses having multiple contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers ([0091], figure 15a, contact wells (#S1-S4) is seen extending through a respective subset of layers of the alternating stack (#32, #42) including a topmost insulating layer #32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani to include a plurality of contact wells as taught by Ishii in order to have an improved signal integrity, enhanced thermal management, and to lower the resistivity of noise.
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Regarding claim 2. Mizutani as modified discloses (noting that with the teaching of Ishii there will be multiple wells similar to the single well of Mizutani) wherein: each of the contact wells comprises a plurality of primary sidewalls each having a respective stepped bottom edge containing at least two horizontally-extending edge segments and at least one vertically-extending edge segment ([0145], figure 18b annotated above, the contact well #269 is seen with a plurality of primary sidewalls #Pri-Side each having a respective stepped bottom edge containing at least two horizontally-extending edge segments #Hor-Ext and at least one vertically-extending edge segment #Ver-Ext); and
each of the primary sidewalls comprises a respective top edge located entirely within a horizontal plane, and the top edges of the primary sidewalls are adjoined to each other to define a top periphery of each of the contact wells ([0145], figure 18b annotated above, the primary sidewalls #Pri-Side comprises of a respective top edge located entirely within a horizontal plane #H1P. and the top edges of the primary sidewalls #Pri-Side define a top periphery).
Regarding claim 3. Mizutani as modified discloses wherein: each of the contact wells comprises a plurality of bottom surface segments that are vertically spaced apart from each other ([0145], figure 18b annotated above, each of the contact wells #269 comprise of a plurality of bottom surface segments that is vertically spaced apart from each other); and
each horizontally-extending edge segment of the stepped bottom edges of each of the contact wells coincides with an edge of a respective bottom surface segment of the plurality of bottom surface segments ([0145], figure 18b annotated above, each of the horizontal-extending edge segment #Hor-Ext of the stepped bottom edges of the contact well #269 coincides with an edge of a respective bottom surface segment of the plurality of bottom surface segments).
Regarding claim 4. Mizutani as modified discloses wherein each of the contact wells comprises a plurality of secondary sidewalls that are not vertically coincident with any of the plurality of primary sidewalls ([0145], figure 18b annotated above, each of the contact wells #269 comprises of a plurality of secondary sidewalls #Sec-Side that is not vertically coincident with any of the plurality of primary sidewalls #Pri-Side).
Regarding claim 9. Mizutani as modified discloses wherein: each of the insulating layers and the electrically conductive layers within the alternating stack comprises lengthwise sidewalls that laterally extend along a first horizontal direction ([0145], figure 18b, each of the insulating layers #32 and electrically conductive layers #46 comprises lengthwise sidewalls that extend laterally a first horizontal direction); and the alternating stack comprises a memory block ([0003], figure 18b, the alternating stack comprises a memory block as described).
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Regarding claim 10. Mizutani as modified discloses wherein: the array of contact via structures comprises N rows of contact via structures arranged along the first horizontal direction ([0145], figure 18b annotated above, an array of contact via structures #286 with N rows of #N1 and #N2 is seen along the first horizontal direction);
each row of contact via structures within the N rows of contact via structures comprises a respective set of M contact via structures ([0145], figure 18b annotated above, each row of contact via structures within the N rows comprises of its own respective set of #M1 and #M2 contact via structures);
M is a first integer greater than 1; and N is a second integer greater than 1 ([0145], figure 18b annotated above, the integers for the N rows of contact via structures and the M contact via structures is greater than 1).
Regarding claim 11. Mizutani as modified discloses wherein the array of contact via structures comprises an M x N rectangular array of contact via structures ([0145], figure 18b annotated above, wherein the array of contact via structures #286 comprises of MxN rectangular array of contact via structures as seen illustrated).
Regarding claim 12. Mizutani as modified discloses wherein: a first one of the dielectric fill structures is in direct contact with each of the insulating layers within the alternating stack that overlies a horizontal plane including a bottommost surface of the first one of the dielectric fill structures ([0145], figure 18b, the dielectric fill structure #165 is in direct contact with the insulating layers #32 that overlies a horizontal plane including the bottommost surface).
Mizutani as modified lacks wherein each of the electrically conductive layers within the alternating stack that overlies the horizontal plane is laterally spaced from the first one of the dielectric fill structures by a vertically-extending portion of a respective backside blocking dielectric layer.
Ishiii discloses wherein each of the electrically conductive layers within the alternating stack that overlies the horizontal plane is laterally spaced from the first one of the dielectric fill structures by a vertically-extending portion of a respective backside blocking dielectric layer ([0149], figure 30, each electrically conductive layer #46 that overlies the horizontal plane is laterally spaced from the dielectric fill structure #65 by a vertically-extending portion of a respective backside blocking dielectric layer #44).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include a backside blocking dielectric layer as taught by Ishii in order to have an greater device integrity, reduced failures in electrical issues, and enhanced thermal management.
Regarding claim 13. Mizutani as modified discloses wherein a first one of the dielectric fill structure is in direct contact with each of the insulating layers and each of the electrically conductive layers within the alternating stack that overlie a horizontal plane including a bottommost surface of the first one of the dielectric fill structures ([0145], figure 18b, the dielectric fill structure #165 is in direct contact with each insulating layer #32 and each electrically conductive layer #46 that overlies a horizontal plane including a bottommost surface of the dielectric fill structure #165).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (US-20220045089-A1 referred as Mizutani) and Ishii et al. (US-20190319040-A1 referred as Ishii) as applied to claim 2, in further view of Wu et al. (US-20220059539-A1 referred as Wu).
Regarding claim 5. Mizutani as modified discloses wherein: the top periphery of each of the contact wells is located entirely within a first horizontal plane including a top surface of a topmost layer within the alternating stack ([0120], figure 18b annotated above, the top periphery of each contact well #269 (more clearly seen in figure 10b, is located entirely within a first horizontal plane #H1p including a top surface of topmost layer within the alternating stack); and
top surfaces of the array of contact via structures are located within a second horizontal plane overlying the first horizontal plane ([0145], figure 18b annotated above, a top surface of the array contact via structure #286 is seen within a second horizontal plane #H2P overlying the first horizontal plane #H1P).
Mizutani as modified lacks a top surface of each of the dielectric fill structures is located entirely within the first horizontal plane.
Wu discloses a top surface of each of the dielectric fill structures is located entirely within the first horizontal plane ([0037], figure 2, the top surface of each dielectric fill structure #202 is entirely within the first horizontal plane seen at the top surface of substrate #201).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include a top surface of each of the dielectric fill structures is located entirely within the first horizontal plane as taught by Wu in order to have an increased protection in the circuits, reduce electrical short circuits, and to optimize the electrical insulation.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (US-20220045089-A1 referred as Mizutani) and Ishii et al. (US-20190319040-A1 referred as Ishii) in further view of Waskiewicz et al. (US-20200075746-A1 referred as Waskiewicz).
Regarding claim 6. Mizutani as modified lacks wherein a first one of the dielectric fill structures located in a first one of the contact wells comprises: at least one dielectric liner located at a peripheral region of the first one of the contact wells; and
a dielectric fill material portion that is laterally surrounded by the at least one dielectric liner, wherein each contact via structure within the array of contact via structures is laterally offset inward from the plurality of primary sidewalls of the first one of the contact wells by a respective lateral offset distance that is greater than a total thickness of the at least one dielectric liner.
Waskiewicz discloses wherein a first one of the dielectric fill structures located in a first one of the contact wells comprises: at least one dielectric liner located at a peripheral region of the first one of the contact wells ([0049], figure 14 with labels seen in figure 12 and figure 1, a dielectric fill structure #120 is located in one of the contact wells #115 which comprises one dielectric liner #140 located at the peripheral region of the contact well #115); and
a dielectric fill material portion that is laterally surrounded by the at least one dielectric liner, wherein each contact via structure within the array of contact via structures is laterally offset inward from the plurality of primary sidewalls of the first one of the contact wells by a respective lateral offset distance that is greater than a total thickness of the at least one dielectric liner ([0049], figure 14 with labels seen in figure 12 and figure 1 and figure 10, a dielectric fill material portion #120 is seen laterally surrounded by atleast one dielectric liner #140 wherein each contact via structure #134 is laterally offset inward from the plurality of primary sidewalls of the first one of the contact wells #115 by a respective lateral offset distance that is greater than a total thickness of the at least one dielectric liner #140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include a dielectric fill material portion that is laterally surrounded by the at least one dielectric liner as taught by Waskiewicz in order to have an increased protection in the circuits, reduce electrical short circuits, and to optimize the electrical insulation.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (US-20220045089-A1 referred as Mizutani), Ishii et al. (US-20190319040-A1 referred as Ishii), and Waskiewicz et al. (US-20200075746-A1 referred as Waskiewicz) as applied to claim 6, in further view of Jhothiraman et al. (US-20210134736-A1 referred as Jhothiraman).
Regarding claim 7. Mizutani as modified discloses wherein: each of the insulating layers has a first thickness ([0145], figure 18b, each insulating layer #32 has a first thickness); each vertically neighboring pair of the insulating layers is vertically spaced from each other by a second thickness ([0145], figure 18b, each neighboring insulating layer #32 is vertically spaced from each other by a second thickness which is vertical).
Mizutani as modified lacks wherein: each contact via structure within the array of contact via structures vertically extends through a respective horizontally-extending portion of the at least one dielectric liner; and the horizontally-extending portions of the at least one dielectric liner are vertically offset from each other by integer multiples of a sum of the first thickness and the second thickness.
Jhothiraman discloses wherein: each contact via structure within the array of contact via structures vertically extends through a respective horizontally-extending portion of the at least one dielectric liner ([0079], figure 12, the two center contact via structures #240 is seen extending through a respective horizontally-extending portion of one dielectric liner #238); and the horizontally-extending portions of the at least one dielectric liner are vertically offset from each other by integer multiples of a sum of the first thickness and the second thickness ([0079], figure 12, the two center contact via structures #240 with its respective horizontally-extending portions of the dielectric liner #238 is seen vertically offset from each other by integer multiples of a sum of the first thickness and second thickness. Please note the first thickness is from the insulating layer #302 with the second thickness being the separation distance from the insulating layers #302 in the stacked structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include each contact via structure within the array of contact via structures vertically extending through a respective horizontally-extending portion of the at least one dielectric liner as taught by Jhothiraman in order to have an enhanced electrical connection for the contact via structure, reduced signal inference, and with additional support for the devices integrity.
Regarding claim 8. Mizutani as modified discloses the dielectric fill material portion comprises silicon oxide ([0133], figure 18b, the dielectric fill material portion #165 is made of silicon oxide).
Mizutani as modified lacks wherein: the at least one dielectric liner comprises a first dielectric liner comprising a silicon oxide material that is in direct contact with the plurality of primary sidewalls of the first one of the contact wells and a plurality of bottom surface segments of the first one of the contact wells, and further comprises a second dielectric liner comprising a dielectric material other than silicon oxide and contacting inner sidewalls of the first dielectric liner.
Jhothiraman discloses wherein: the at least one dielectric liner comprises a first dielectric liner comprising a silicon oxide material that is in direct contact with the plurality of primary sidewalls of the first one of the contact wells and a plurality of bottom surface segments of the first one of the contact wells ([0079, 0084], figure 12, the dielectric liner further includes a first dielectric liner #238 (which comprises of silicon oxide) that is in direct contact with the plurality of primary sidewalls of the contact well #502 (labeled in fig 5) and also the plurality of bottom surface segments), and further comprises a second dielectric liner comprising a dielectric material other than silicon oxide and contacting inner sidewalls of the first dielectric liner ([0079, 0084], figure 12, the second dielectric liner #904 (comprises of material other than silicon oxide as described in [0074]) is seen contacting the inner sidewalls of the first dielectric liner #238).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include a first and second dielectric liner as taught by Jhothiraman in order to have an increased protection in the circuits, reduce electrical short circuits, and to optimize the electrical insulation.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Mizutani et al. (US-20220045089-A1 referred as Mizutani) and Ishii et al. (US-20190319040-A1 referred as Ishii) in further view of Jhothiraman et al. (US-20210134736-A1 referred as Jhothiraman).
Regarding claim 14. Mizutani as modified lacks wherein the contact wells are separated by different distances from each other.
Jhothiraman discloses wherein the contact wells are separated by different distances from each other ([0041], figure 2, the contact wells #240 are separated by different distances from each other. More specifically, the distance from the left #240 to the middle left #240 is greater than the distance from the middle left #240 to the middle right #240.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Mizutani as modified to include contact wells are separated by different distances from each other as taught by Jhothiraman in order to distribute weight across the device, increase the devices integrity, and to allow for enhanced contact well accessibility.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Pachamuthu et al. (US-20150236038-A1) and Tanaka et al. (US-20220005824-A1) for teaching the contact wells, alternating stacks, and the memory structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818