Prosecution Insights
Last updated: October 02, 2026
Application No. 18/360,470

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jul 27, 2023
Priority
Aug 19, 2022 — JP 2022-131066
Examiner
DIAZ, JOSE R
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
2 (Non-Final)
87%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
841 granted / 967 resolved
+19.0% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
21 currently pending
Career history
977
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
33.8%
-6.2% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 967 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on July 24, 2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Poddar et al. (US 2021/0202357), cited by Applicant. Regarding claim 1, Poddar discloses a semiconductor device comprising: a first lead (23/24) having a die pad (22) [Figs. 1C-1E]; a second lead (23/25) arranged to be spaced apart from the first lead (23/24) [Figs. 1C-1E]; a first semiconductor element (40) mounted on the die pad (22) [Figs. 1C-1E]; a second semiconductor element (50) mounted on the die pad (22) [Figs. 1C-1E]; and a plurality of wires (35) electrically connected to the first semiconductor element (40) and the second lead (23/25) [Figs. 1C-1E], wherein the die pad (22) and the second lead (23/25) are arranged side by side in a first direction (x) [Fig. 1D, annotated below] perpendicular to a thickness direction (z) [Fig. 1E, annotated below], wherein all of the plurality of wires (35) are inclined with respect to the first direction (x) when viewed in the thickness direction (z) [Figs. 1D-1E], wherein the die pad (22) has a die pad main surface (top surface), which faces a first side (top portion) in the thickness direction (z) and on which the first semiconductor element (40) and the second semiconductor element (50) are mounted [Figs. 1D-1E], wherein the second semiconductor element (50) is arranged on a first side (lateral portion) in the first direction (x) [Figs. 1D-1E], which is opposite to the second lead (23/25) with respect to the first semiconductor element (40) in the first direction (x) [Figs. 1D-1E], and wherein the second semiconductor element (50) is a drive element that drives the first semiconductor element (40) [paragraphs 0029-0031]. [AltContent: textbox (FF)][AltContent: textbox (FF)][AltContent: arrow][AltContent: textbox (B1)][AltContent: arrow][AltContent: textbox (B2)][AltContent: connector][AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: textbox (NB)][AltContent: textbox (NB)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (y)][AltContent: textbox (x)][AltContent: arrow][AltContent: arrow][AltContent: textbox (x)][AltContent: arrow][AltContent: textbox (z)] PNG media_image1.png 1004 632 media_image1.png Greyscale Regarding claim 2, Poddar discloses: wherein each of the plurality of wires (35) includes a first bonding portion (B1) bonded to the first semiconductor element (40) and a second bonding portion (B2) bonded to the second lead (23/25) [Figs. 1D-1E, annotated above; and paragraphs 0029 and 0057], and wherein the first bonding portion (B1) is located on a first side (lateral portion) in a second direction (y), which is perpendicular to the thickness direction (z) and the first direction (x), from the second bonding portion [Figs. 1D-1E, annotated above; and paragraphs 0029 and 0057]. Regarding claim 3, Poddar discloses: wherein the second lead (23/25) has a second lead main surface (along the cross-sectional line FF) facing a first side (lateral portion) in the thickness direction (y), wherein the second lead main surface (along the cross-sectional line FF) includes a bonding region (B2) to which the plurality of wires (35) is bonded and a non-bonding region (NB) to which the wires are not bonded [Figs. 1E-1E, annotated above], and wherein the non-bonding region (NB) is arranged on the first side (lateral portion) in the second direction (y) of the bonding region (B2). Regarding claim 6, Poddar discloses: wherein each of the plurality of wires (35) is curved in a second direction (y), which is perpendicular to the thickness direction (z) and the first direction (x) [Figs. 1D-1E, annotated above]. Regarding claim 7, Poddar discloses: wherein the second lead (23/25) has a through-hole (H) penetrating in the thickness direction (z) [Fig. 1C, annotated below]. [AltContent: textbox (H)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow] PNG media_image2.png 712 868 media_image2.png Greyscale Regarding claim 8, Poddar discloses wherein the first semiconductor element (40) is a switching element [Fig. 2 and paragraph 0043]. Regarding claim 9, Poddar discloses wherein the first semiconductor element contains GaN [paragraph 0039]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Poddar et al. (US 2021/0202357). Regarding claim 4, Poddar discloses wherein a first dimension (D1) of the bonding region in the second direction (y) is 40% or more and 60% or less of a second dimension (D2) of the second lead (25) in the second direction (y) [See Fig. 1D, annotated below]. [AltContent: textbox (D2f)][AltContent: textbox (D2e)][AltContent: textbox (D2d)][AltContent: textbox (D2c)][AltContent: textbox (D2b)][AltContent: textbox (D2a)][AltContent: textbox (D1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: connector] PNG media_image3.png 712 662 media_image3.png Greyscale Please note that the dimension D1 is equal to about 4/6 (i.e. D2b-D2e) of the total dimension D2 (i.e. D2a-D2f). The court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Poddar et al. (US 2021/0202357) in view of Washida et al. (JP 10012790 A), cited by Applicant. Regarding claim 5, Poddar is silent with respect to limitation about dummy leads. Washida teaches dummy leads (1) respectively arranged on both sides of the second lead in a second direction, which is perpendicular to the thickness direction and the first direction [Fig. 1 and English Translation, Section: “Solution” and paragraph 15]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Poddar by including dummy leads as taught by Washida because it helps to improve mechanical and thermal resistance reliability [ English Translation, Section: “Problem to be Solved”]. Allowable Subject Matter Claim 11 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: In regards to claim 11, the prior art fails to teach, disclose, or suggest, either alone or in combination, the limitations: a second wire electrically connected to the first semiconductor element and the die pad main surface; wherein the die pad includes an opening having an open end on the die pad main surface and partitioning the first region, the second region, and the third region as instantly claimed, and in combination with the additional limitations. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pang et al. (US 10037935) teaches dummy leads (520) in Fig. 5. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jul 27, 2023
Application Filed
Dec 31, 2025
Non-Final Rejection mailed — §102, §103
Mar 25, 2026
Response Filed
Jul 24, 2026
Request for Continued Examination
Aug 24, 2026
Response after Non-Final Action
Aug 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.9%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 967 resolved cases by this examiner. Grant probability derived from career allowance rate.

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