DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 11/17/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 14 recite “a sidewall structure covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, of a first end of the silicon contact structure proximate to the metal silicide layer.”
The term "proximate" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Proximate” is defined as "very near : close” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how close the layer needs to be in order to meet the requirements of “proximate.”
The term “proximate” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is nanometers, and possible values of distance), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Therefore, claims 1 and 14 are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, and claims 2-13 are rejected for at least their dependencies. Appropriate correction is required.
For the purposes of examination, any distance of separation between the layers will be considered “proximate.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-8, and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220336465 A1, hereinafter Kim)
With regards to claim 1, Kim discloses a semiconductor device, (FIG. 2) comprising:
a silicon contact structure; (at least direct contact DC/conductive layer 130, Paragraph [0033]: ‘the lower conductive layer 130 may include or be formed of a doped polysilicon layer.”)
a metal silicide layer (conductive layer 132, Paragraph [0033]: “The intermediate conductive layer 132 and the upper conductive layer 134 may each include or may be …tungsten silicide (WSix)…”) on one side of the silicon contact structure; (See FIG. 2)
a bit line structure (conductive layer 134) located on the side of the metal silicide layer away from the silicon contact structure and extending in a first direction; (see FIG. 2, showing the layer 134 away from layer 130) and
a sidewall structure (at least spacer 142/174) covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, (Z direction) of a first end of the silicon contact structure proximate to the metal silicide layer. (See FIG. 2, showing the spacer 142 covering sidewalls of 130-134)
With regards to claim 2, Kim discloses the semiconductor device of claim 1, wherein the sidewall structure extends continuously in the first direction. (See FIG. 2, showing the continuous extension)
With regards to claim 3, Kim discloses the semiconductor device of claim 1, wherein the sidewall structure is in contact with the opposite sides of the metal silicide layer in the first direction and with the opposite sides of the first end in the first direction. (See FIG. 2, showing the contacting)
With regards to claim 5, Kim discloses the semiconductor device of claim 1, wherein the semiconductor device further comprises an insulating layer (at least air gap 146) on the opposite sides of the sidewall structure and the opposite sides of the silicon contact structure in the first direction. See Fig 2, showing the placement of the air gap 146)
With regards to claim 6, Kim discloses the semiconductor device of claim 5, wherein a portion of the insulating layer corresponding to the bit line structure has air gaps therein. (Paragraph [0146]: “The intermediate insulating spacer 146 may include or may be a silicon oxide layer/pattern, an air spacer…”)
With regards to claim 7, Kim discloses the semiconductor device of claim 5, wherein a material of the sidewall structure has a different etching selection ratio from the material of a portion of the insulating layer corresponding to the silicon contact structure. (see FIG. 2, where the TiN of the spacer 174/142 has a different etch selection ratio to the polysilicon contact 130)
With regards to claim 8, Kim discloses the semiconductor device of claim 7, wherein the material of the sidewall structure comprises titanium nitride. (Paragraph [0039]: “the conductive barrier layer 174 may have a Ti/TiN stack structure…”)
With regards to claim 13, Kim discloses the semiconductor device of claim 1, wherein the silicon contact structure comprises a polysilicon layer and a single crystal silicon layer (single crystal portion of substrate 110 directly below direct contact DC/layer 130, see Paragraph [0027])) with the polysilicon layer located between the single crystal silicon layer and the metal silicide layer. (See FIG. 2)
With regards to claim 14, Kim discloses a memory system, (integrated circuit, see Abstract and FIG. 2) comprising:
a semiconductor device, (device 100) comprising:
a silicon contact structure; (direct contact DC/conductive layer 130, Paragraph [0033]: ‘the lower conductive layer 130 may include or be formed of a doped polysilicon layer.”)
a metal silicide layer (conductive layer 132, Paragraph [0033]: “The intermediate conductive layer 132 and the upper conductive layer 134 may each include or may be …tungsten silicide (WSix)…”) on one side of the silicon contact structure; (See FIG. 2)
a bit line structure (conductive layer 134) located on the side of the metal silicide layer away from the silicon contact structure and extending in a first direction; (see FIG. 2, showing the layer 134 away from layer 130) and
a sidewall structure (at least spacer 142/174) covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, (Z direction) of a first end of the silicon contact structure proximate to the metal silicide layer. (See FIG. 2, showing the spacer 142 covering sidewalls of 130-134) and
a controller coupled with and used to control the semiconductor device. (Examiner takes official notice that all semiconductor/memory devices are operated by a controller of some form, either using voltage switching or some other program)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220336465 A1, hereinafter Kim) in view of Kim et al. (US 20200111512 A1, hereinafter Kim2)
With regards to claim 12, Kim discloses the semiconductor device of claim 1.
However, Kim does not explicitly teach wherein a material of the metal silicide layer comprises at least one of titanium silicide, cobalt silicide, nickel silicide and platinum silicide.
Kim2 teaches that tungsten silicide and at least cobalt silicide are equivalent materials for creating a conductive material. (Paragraph [0041]: “The first conductive lines CL1 may include a conductive material. For example, the conductive material may include… a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.)…”)
It would have been obvious to one of ordinary skill in the art to modify the device of Kim to have the materials of Kim2, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that using cobalt silicide is substituting one known element for another in order to obtain predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (US 20210035613 A1) – Using silicide and polysilicon for a bit line structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812