Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species A in the reply filed on 11/20/25 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/20/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tobioka (US PGPub 2022/0328403).
Claim 1: Tobioka teaches (Fig. 1B, 1E, 13H, 23B) a three-dimensional memory device, comprising: insulating layers (132,232) that are vertically spaced apart from each other and that continuously laterally extend between a first first-type lateral isolation trench fill structure (76) and a second first-type lateral isolation trench fill structure (76) that laterally extend along a first horizontal direction (hd1) (Fig. 1B)and laterally spaced apart from each other along a second horizontal direction (hd2) (Fig. 1E); first electrically conductive layers (146) vertically interlaced with the insulating layers and contacting the first first-type lateral isolation trench fill structure; second electrically conductive layers (246) vertically interlaced with the insulating layers and contact the second first-type lateral isolation trench fill structure; and a composite dielectric isolation structure located between the first electrically conductive layers and the second electrically conductive layers and comprising a retro-stepped dielectric material portion (165, 265) a vertical stack of dielectric material plates (130,230) (Fig. 13H), and a pair of second-type lateral isolation trench fill structures (76) that are laterally spaced apart along the first horizontal direction.
Claim 2: Tobioka teaches (Fig. 13H, 23B) the retro-stepped dielectric material portion has a first lateral extent along the second horizontal direction; and each dielectric material plate in the vertical stack of dielectric material plates has a second lateral extent along the second horizontal direction that is less than the first lateral extent.
Claim 3: Tobioka teaches (Fig. 13H, 23B) the dielectric material plates within the vertical stack of dielectric material plates have lateral extents along the first horizontal direction that decrease with a vertical distance from a horizontal plane including a bottommost surface of the vertical stack.
Claim 4: Tobioka teaches (Fig. 13H, 23B) each dielectric material plate within the vertical stack of dielectric material plates has a respective sidewall that is parallel to the second horizontal direction and contacts a respective vertical sidewall segment of the retro-stepped dielectric material portion.
Claim 9: Tobioka teaches (Fig. 13H, 23B) the retro-stepped dielectric material portion has a first variable lateral extent along the first horizontal direction that increases stepwise with a vertical distance from a horizontal plane including a bottommost surface of the vertical stack.
Claim 10: Tobioka teaches (Fig. 13H, 23B) the retro-stepped dielectric material portion has a second variable lateral extent along the second horizontal direction that increases gradually without any step along the second horizontal direction.
Claim 13: Tobioka teaches (Fig. 1C) first memory openings extending through a first alternating stack of the first electrically conductive layers vertically interlaced with the insulating layers; second memory openings extending through a second alternating stack of the second electrically conductive layers vertically interlaced with the insulating layers; and memory opening fill (58) [0085]structures located in the first and the second memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tobioka (US PGPub 2022/0328403), as applied to claim 1 above, and further in view of Iwai et al. (US PGPub 2021/0384206).
Regarding claim 5, as described above, Tobioka substantially read on the invention as claimed, except Tobioka does not teach each dielectric material plate within the vertical stack of dielectric material plates comprises a concave sidewall segment located at a same level as a respective electrically conductive layer selected from the first electrically conductive layers and the second electrically conductive layers, and is in contact with a convex sidewall segment of a structural element selected from the respective electrically conductive layer or a backside blocking dielectric layer that contacts the respective electrically conductive layer. Iwai teaches ((Fig. 17B, 18A) each dielectric material plate (152, 252) within the vertical stack of dielectric material plates comprises a concave sidewall segment [0217] located at a same level as a respective electrically conductive layer (246) selected from the first electrically conductive layers and the second electrically conductive layers, and is in contact with a convex sidewall segment of a structural element selected from the respective electrically conductive layer or a backside blocking dielectric layer that contacts the respective electrically conductive layer (Fig. 22C). Iwai teaches the concave sidewalls being an alternate option for the plates providing support in a vertical memory stack (ABS, [0217]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the plates taught by Tobioka to have a concave sidewall as it is a known option to straight sidewalls as taught by Iwai (ABS, [0217]).
Claim 11: Iwai teaches ((Fig. 17B, 18A) a dielectric material plate within the vertical stack of dielectric material plates comprises: first sidewall segments laterally extending along the first horizontal direction and contacting one of the second-type lateral isolation trench fill structures; a second sidewall segment laterally extending along the second horizontal direction and contacting the one of the second-type lateral isolation trench fill structures; a first concave surface segment located at a level of one of the first electrically conductive layers and in contact with a convex sidewall of a first structural element that is selected from the one of the first electrically conductive layers and a first blocking dielectric layer that contacts the one of the first electrically conducive layers; and a third sidewall segment laterally extending along the first horizontal direction and in contact with a planar sidewall of the first structural element.
Claim 12: Iwai teaches ((Fig. 17B, 18A) a plurality of dielectric material plates within the vertical stack of dielectric material plates has a uniform width along the second horizontal direction that is less than a minimum lateral dimension of the retro-stepped dielectric material portion along the second horizontal direction 6. The three-dimensional memory device of Claim 5, wherein each dielectric material plate within the vertical stack of dielectric material plates further comprises: a first planar sidewall segment in contact with a planar sidewall segment of a first etch stop liner that contacts a second-type lateral isolation trench fill structure of the pair of second-type lateral isolation trench fill structures; and a second planar sidewall segment in contact with a planar sidewall segment of the structural element.
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814