DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 5/13/2026 in which claims 1, 8, and 14 were amended.
Claims 1-20 remain pending and are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 8, 11-15, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al (US 2021/0217701 and Huang hereinafter).
As to claims 1, 2, 5: Huang discloses [claim 1] a stack of semiconductor dies (Figs. 1 and 4C; 110, 120, and 130; [0024] and [0028]) for a semiconductor package (100; [0024]), comprising: a first semiconductor die (110; [0024] and [0028]); a second semiconductor die (120; [0024] and [0028]) stacked on top of the first semiconductor die (110), the first semiconductor die (100) and the second semiconductor die (120) defining a step corner (C1; [0035]) between a surface (110a; [0035]) of the first semiconductor die (110) and a sidewall (120s; [0035]) of the second semiconductor die (120); a step ramp (160; [0024]) formed in the step corner (C1) and forming a slope (the outer edge of 160 is sloped) that extends between (“extends between” is interpreted to mean -to span a distance in a space separating two objects or regions-, as 160 and its associated slope/outer edge exists between/along an imaginary line that extends from the top surface 110a of the first semiconductor die 110 to the top surface 120s of the second semiconductor die 120, the slope and 160 extends between the top surfaces of the two dies) the surface (110a) of the first semiconductor die (110) and a top surface (120s) of the second semiconductor die (120); and a transmission line (210/411 and 412; [0024] and [0051]) formed on a first bond pad (111; [0025]) associated with the first semiconductor die (110), the step ramp, (160) and a second bond pad (121; [0026]) associated with the second semiconductor die (120), wherein the transmission line (210/411 and 412) electrically connects ([0029]) the first bond pad (111) and the second bond pad (121); [claim 2] wherein the step ramp (160) is formed from a polymer (polyimide; [0039]); [claim 5] further comprising a metal coating (413; [0051]-[0052]) provided over the transmission line (210/411 and 412), the first bond pad (111) and the second bond pad (121); [claim 6] wherein the metal coating (413) is copper (the conductive layer 210 can be copper and the seed layer 412 of transmission layer can be copper and 413 is referred to as a conductive layer, which Examiner interprets that 413 can be copper as well from the list of conductive layers of [0031]; [0031] and [0052]).
As to claims 8 and 11-13: Huang discloses [claim 8] a method for assembling a stack of semiconductor dies (110, 120, and 130; [0058]) for a semiconductor package (Figs. 6A-6L), comprising: stacking a second semiconductor die (Fig. 6A; 120; [0058]) on a first semiconductor die (110) to form the stack of semiconductor dies, the first semiconductor die (110) and the second semiconductor die (120) defining a step corner (Fig. 1; C1; [0035]) between a surface (110a; [0035]) of the first semiconductor die (110) and a sidewall (120s; [0035]) of the second semiconductor die (120); forming a step ramp (Fig 6D; 160; [0061]) in the step corner (C1), the step ramp (160) forming a slope (the outer edge of 160 is sloped) that extends between (“extends between” is interpreted to mean -to span a distance in a space separating two objects or regions-, as 160 and its associated slope/outer edge exists between/along an imaginary line that extends from the top surface 110a of the first semiconductor die 110 to the top surface 120s of the second semiconductor die 120, the slope and 160 extends between the top surfaces of the two dies) the surface (110a) of the first semiconductor die (110) and a top surface (120s) of the second semiconductor die (120); and forming a transmission line (Fig. 6E; 520; [0062]) over a first bond pad (111; [0058] and [0062]) associated with the first semiconductor die (110), the step ramp, (160) and a second bond pad (121; [0058] and [0062]) associated with the second semiconductor die (120), wherein the transmission line (520) electrically connects ([0029]) the first bond pad (111) and the second bond pad (121); [claim 11] further comprising forming a metal coating (Fig. 6I; 540; [0066]) over at least a portion of the transmission line (520), the first bond pad (111) and the second bond pad (121); [claim 12] wherein the metal coating (540) is copper (the conductive layer 210 can be copper and the seed layer 520 of transmission layer can be copper and 540 is referred to as a conductive layer, which Examiner interprets that 540 can be copper as well from the list of conductive layers of [0031]; [0031] and [0066]); [claim 13] wherein the step ramp (160) is formed from a polymer (polyimide; [0039]).
As to claims 14, 15, 18, and 19: Huang discloses [claim 14] a stack of semiconductor dies (Figs. 1 and 4C; 110, 120, and 130; [0024]) for a semiconductor package (100; [0024]), comprising: a first semiconductor die (110; [0024]); a second semiconductor die (120; [0024]) stacked on top of the first semiconductor die (110), the first semiconductor die (110) and the second semiconductor die (120) defining a step corner (C1; [0035]) between a surface (110a; [0035]) of the first semiconductor die (110) and a sidewall (120s; [0035]) of the second semiconductor die (120); a ramp means (160; [0036]) formed in the step corner (C1) and forming a slope (the outer edge of 160 is sloped) that extends between (“extends between” is interpreted to mean -to span a distance in a space separating two objects or regions-, as 160 and its associated slope/outer edge exists between/along an imaginary line that extends from the top surface 110a of the first semiconductor die 110 to the top surface 120s of the second semiconductor die 120, the slope and 160 extends between the top surfaces of the two dies) the surface (110a) of the first semiconductor die (110) and a top surface (120s) of the second semiconductor die (120); and a transmission means (210/411 and 412; [0029] and [0052]) formed on a first connection means (111; [0025]) associated with the first semiconductor die (110), the ramp means (160) and a second connection means (121) associated with the second semiconductor die (120), wherein the transmission means (210/411 and 412) electrically connects ([0029]) the first connection means (111) and the second connection means (121) connection means of the first semiconductor die (110) and the second semiconductor die (120); [claim 15] wherein the ramp means (160) is formed from a polymer (polyimide; [0039]); [claim 18] further comprising a coating means (413; [0052]) provided over the transmission means (411 and 412), the first connection means (111) and the second connection means (121); [claim 19] wherein the coating means (413) is comprised of copper (the conductive layer 210 can be copper and the seed layer 412 of transmission layer can be copper and 413 is referred to as a conductive layer, which Examiner interprets that 413 can be copper as well from the list of conductive layers of [0031]; [0031] and [0052]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 4, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Cho et al (US 2004/0155322 and Cho hereinafter).
As to claims 3 and 4: Although the structure disclosed by Huang shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
[claim 3] wherein the step ramp forms an approximate forty-five degree angle between the surface of the first semiconductor die and the sidewall of the second semiconductor die; [claim 4] wherein the step ramp forms less than a forty-five degree angle between the surface of the first semiconductor die and the sidewall of the second semiconductor die.
Huang discloses the step ramp 160 but fails to expressly disclose the angle of the incline of the step ramp 160 that is used to aid in forming the transmission line 210/411 and 412.
Cho discloses in Fig. 1 a die 10 with a step ramp 40 adjacent the sidewall 16 of the die 10 that aids in forming the transmission line 50 from the bonding pad 12 of the die 10 to a lower semiconductor structure, see [0033]-[0039].
Cho discloses [claim 3] wherein the step ramp (Fig. 1; 40; [0038]) forms an approximate forty-five degree angle (angle of the incline can be between 30 and 75 degrees; [0039]) between the surface of the first semiconductor die and the sidewall of the second semiconductor die (10; [0038]); [claim 4] wherein the step ramp (40) forms less than a forty-five degree angle (angle of the incline can be between 30 and 75 degrees; [0039]) between the surface of the first semiconductor die and the sidewall of the second semiconductor die (10).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the angle of the incline of the step ramp 160 of Huang using the angle of incline teaching of Cho to arrive at an angle of either 45 degrees or less than 45 degrees as the angle of incline of Cho overlaps with the claimed ranges in order to provide step ramp that allows for improved attachment and prevent shorts of the transmission line 210/411 and 412 of Huang (and 50 of Cho), see [0039]. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.”
As to claims 16 and 17: Although the structure disclosed by Huang shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
[claim 16] wherein the ramp means forms an approximate forty-five degree angle between the surface of the first semiconductor die and the sidewall of the second semiconductor die; [claim 17] wherein the ramp means forms less than a forty-five degree angle between the surface of the first semiconductor die and the sidewall of the second semiconductor die.
Huang discloses the step ramp 160 but fails to expressly disclose the angle of the incline of the step ramp 160 that is used to aid in forming the transmission line 210/411 and 412.
Cho discloses in Fig. 1 a die 10 with a step ramp 40 adjacent the sidewall 16 of the die 10 that aids in forming the transmission line 50 from the bonding pad 12 of the die 10 to a lower semiconductor structure, see [0033]-[0039].
Cho discloses [claim 16] wherein the ramp means (Fig. 1; 40; [0038]) forms an approximate forty-five degree angle (angle of the incline can be between 30 and 75 degrees; [0039]) between the surface of the first semiconductor die and the sidewall of the second semiconductor die (10; [0038]); [claim 17] wherein the ramp means (40) forms less than a forty-five degree angle (angle of the incline can be between 30 and 75 degrees; [0039]) between the surface of the first semiconductor die and the sidewall of the second semiconductor die (10).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the angle of the incline of the step ramp 160 of Huang using the angle of incline teaching of Cho to arrive at an angle of either 45 degrees or less than 45 degrees as the angle of incline of Cho overlaps with the claimed ranges in order to provide step ramp that allows for improved attachment and prevent shorts of the transmission line 210/411 and 412 of Huang (and 50 of Cho), see [0039]. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.”
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Weiss et al (US 2021/0104464 and Weiss hereinafter).
As to claim 7: Although the structure disclosed by Huang shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
wherein the first semiconductor die is associated with a plurality of bond pads and wherein each of the plurality of bond pads have a pitch of approximately thirty micrometers (µm).
Huang discloses semiconductor dies that can be used in different applications.
Weiss discloses that semiconductor dies can have high density interconnect (HDI) regions that comprise a plurality of bond pads where the bond pads can have a pitch between 10 and 100 microns, see [0050].
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the pitch between a plurality of bond pads to be 30 microns as the range of Weiss discloses a range for the pitch that overlaps with the claimed value in order to provide improved and fast communication between chips and external devices by decreasing the pitch size and increasing the number of bond pads, see [0002]. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.”
As to claim 20: Although the structure disclosed by Huang shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
wherein the first semiconductor die is associated with a plurality of connection means and wherein each of the plurality of connection means have a pitch of approximately thirty micrometers (µm).
Huang discloses semiconductor dies that can be used in different applications.
Weiss discloses that semiconductor dies can have high density interconnect (HDI) regions that comprise a plurality of bond pads where the bond pads can have a pitch between 10 and 100 microns, see [0050].
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the pitch between a plurality of bond pads to be 30 microns as the range of Weiss discloses a range for the pitch that overlaps with the claimed value in order to provide improved and fast communication between chips and external devices by decreasing the pitch size and increasing the number of bond pads, see [0002]. Further, as stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.”
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Yamagishi (JP 3754171 and Yamagishi hereinafter; a machine translation is used as an English language equivalent).
As to claims 9 and 10: Although the method disclosed by Huang shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
[claim 9] further comprising providing a photoresist layer over the step ramp, the first bond pad and the second bond pad prior to forming the transmission line; [claim 10] further comprising preparing the first bond pad and the second bond pad for the transmission line using a laser lithography process based, at least in part, on providing the photoresist layer over the first bond pad and the second bond pad.
Huang discloses in Fig. 6C that before the transmission line 520 is formed, a photomask is used to etch the step ramp (polyimide) material 510.
Yamagishi discloses in Figs. 3(a)-3(c) that a polyimide layer 47a formed over a conductive pad 42a can be patterned to expose the conductive pad 42a using a photoresist layer 49 over the polyimide layer 47a then using a laser (and thus a laser lithography process as a photoresist and laser are used) to expose the conductive pad 42a to allow a conductive line 51b be formed thereon, see [0037]-[0040].
Therefore, a person having ordinary skill in the art would have had it within their ordinary capabilities to use the method of patterning a polyimide film over a conductive pad to expose the conductive pad to allow for a connection to be made thereto using a laser lithography process and a photoresist as done in Yamagishi to pattern the polyimide step ramp material 510 of Huang as the process was well known in the art and applied to the same material in a similar structure and would have yielded the predictable results of selectively patterning the polyimide film to allow for further electrical connections to be made.
Response to Arguments
Applicant's arguments filed 5/13/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that Huang fails to teach or suggest that the step ramp forms a slope that extends between the surface of the first semiconductor die and a top surface of the second semiconductor die. The supporting structure 160 of Huang is designed to fill the corner with a concave surface to prevent cracking-not to provide a slope extending to the top surface of the second semiconductor device. Huang’s supporting structure 160 does not form a slope that extends to the top surface of the second semiconductor device.
Examiner respectfully traverses applicant’s remarks. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that the slope extends to (emphasis added) the top surface of the second semiconductor device) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claim language states that the slope “extends between” the surface of the first semiconductor die and a top surface of the semiconductor die, not that it extends “to”. “Extends between” is interpreted to mean -to span a distance in a space separating two objects or regions-. As the supporting structure/step ramp 160 and its associated slope/outer edge exists along an imaginary line that extends from the top surface 110a of the first semiconductor die 110 to the top surface 120s of the second semiconductor die 120, the slope and step ramp 160 extend between the top surfaces of the two dies.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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