DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A in the reply filed on 24 November 2025 is acknowledged. Claims 17 and 18 have been withdrawn as reading on non-elected Species B. Claim 24 is withdrawn as reading on the non-elected Invention II.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 27 July 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-10, 13-14, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Tonegawa et al (US 20250221070 A1, hereinafter “Tonegawa”), in view of Hashiguchi (US 20250072150 A1, hereinafter “Hashiguchi”).
Regarding Claim 1 – Tonegawa discloses a photoelectric conversion apparatus comprising: a first member (10 [0064] and Figs. 1 and 22) including a photoelectric conversion unit (12 [0064] and Fig. 1) and a transfer transistor in a first semiconductor layer (TR [0070] and Fig. 22), the transfer transistor being configured to transfer an electric charge generated in the photoelectric conversion unit ([0072]); a second member (20 [0065] and Figs. 1 and 22) including a readout circuit in (22 [0065] and Fig. 1) a second semiconductor layer (21 [0065] and Figs. 1 and 22), the readout circuit being configured to output a signal based on the electric charge transferred from the transfer transistor ([0071]); and a third member (30 [0066] and Figs. 1 and 22) including a signal processing circuit (34 [0066] and Fig. 1) in a third semiconductor layer (31 [0066] and Figs. 1 and 22), the signal processing circuit being configured to process the signal ([0067]), wherein a first wiring structure (17 and 18 [0076] and Fig. 22) included in the first member is disposed between the first semiconductor layer and the second semiconductor layer ([0079] and Fig. 3), and a second wiring structure included in the second member (56 [0168] and Fig. 22) and a third wiring structure included in the third member (62 [0169] and Fig. 22) are stacked between the second semiconductor layer and the third semiconductor layer (Fig. 22), wherein the readout circuit is configured to output the signal from the second member to the third member via an output line disposed in the second wiring structure (24 [0072] and Figs. 1 and 22).
Tonegawa fails to disclose a source region or a drain region of a transistor forming the readout circuit includes a salicide structure, and a diffusion prevention layer is disposed between the first semiconductor layer and the second semiconductor layer, the diffusion prevention layer preventing diffusion of metal included in the salicide structure.
However, Hashiguchi discloses a source region or a drain region of a transistor forming the readout circuit includes a salicide structure (salicide on source and drain of 26 in second member 20, which outputs to logic circuit 32 Hashiguchi [0232] and Fig. 36), and a diffusion prevention layer (122 applied to the wiring structure in 20, wherein second substrate 20 is bonded to third substrate 30 Hashiguchi [0108], [0123] and Figs. 1 and annotated 4) is disposed between the first semiconductor layer and the second semiconductor layer (in the wiring structure 100 Hashiguchi [0101] and Fig. 1), the diffusion prevention layer preventing diffusion of metal (Hashiguchi [0108] and Fig. 1).
Hashiguchi discloses a similar photoelectric conversion apparatus to Tonegawa. Hashiguchi teaches including salicide on the source and drain of a transistor in the readout circuit for the benefit of increased calculation speed in the logic circuit (Hashiguchi [0232]). Hashiguchi further teaches a diffusion prevention layer between the first semiconductor layer and the second semiconductor layer for the benefit of preventing diffusion of both metal and water (Hashiguchi [0108]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Tonegawa and Hashiguchi to include salicide on the source and drain of a transistor in the readout circuit for the benefit of increased calculation speed in the logic circuit and to include a diffusion prevention layer between the first semiconductor layer and the second semiconductor layer for the benefit of preventing diffusion of both metal and water.
PNG
media_image1.png
728
457
media_image1.png
Greyscale
PNG
media_image2.png
690
483
media_image2.png
Greyscale
PNG
media_image3.png
639
608
media_image3.png
Greyscale
PNG
media_image4.png
233
350
media_image4.png
Greyscale
PNG
media_image5.png
430
597
media_image5.png
Greyscale
PNG
media_image6.png
650
547
media_image6.png
Greyscale
Regarding Claim 2 – Tonegawa discloses a photoelectric conversion apparatus comprising: a first member (10 [0064] and Figs. 1 and 22) including a photoelectric conversion unit (12 [0064] and Fig. 1) and a transfer transistor in a first semiconductor layer (TR [0070] and Fig. 22), the transfer transistor being configured to transfer an electric charge generated in the photoelectric conversion unit ([0072]); a second member (20 [0065] and Figs. 1 and 22) including a readout circuit in (22 [0065] and Fig. 1) a second semiconductor layer (21 [0065] and Figs. 1 and 22), the readout circuit being configured to output a signal based on the electric charge transferred from the transfer transistor ([0071]); and a third member (30 [0066] and Figs. 1 and 22) including a signal processing circuit (34 [0066] and Fig. 1) in a third semiconductor layer (31 [0066] and Figs. 1 and 22), the signal processing circuit being configured to process the signal ([0067]), wherein a first wiring structure (17 and 18 [0076] and Fig. 22) included in the first member is disposed between the first semiconductor layer and the second semiconductor layer ([0079] and Fig. 3), and a second wiring structure included in the second member (56 [0168] and Fig. 22) and a third wiring structure included in the third member (62 [0169] and Fig. 22) are stacked between the second semiconductor layer and the third semiconductor layer (Fig. 22), wherein the readout circuit is configured to output the signal from the second member to the third member via an output line disposed in the second wiring structure (24 [0072] and Figs. 1 and 22).
Tonegawa fails to disclose a source region or a drain region of a transistor forming the readout circuit includes a silicide structure, the silicide structure being in contact with an insulating film included in the second wiring structure, and a diffusion prevention layer is disposed between the first semiconductor layer and the second semiconductor layer, the diffusion prevention layer preventing diffusion of metal included in the silicide structure.
However, Hashiguchi discloses a source region or a drain region of a transistor forming the readout circuit includes a silicide structure (silicide on source and drain of 26 in second member 20, which outputs to logic circuit 32 Hashiguchi [0232] and Fig. 36), the silicide structure being in contact with an insulating film included in the second wiring structure (51 Hashiguchi [0135] and Fig. 36), and a diffusion prevention layer (122 applied to the wiring structure in 20, wherein second substrate 20 is bonded to third substrate 30 Hashiguchi [0108], [0123] and Figs. 1 and annotated 4) is disposed between the first semiconductor layer and the second semiconductor layer (in the wiring structure 100 Hashiguchi [0101] and Fig. 1), the diffusion prevention layer preventing diffusion of metal (Hashiguchi [0108] and Fig. 1).
Hashiguchi discloses a similar photoelectric conversion apparatus to Tonegawa. Hashiguchi teaches including silicide on the source and drain of a transistor in the readout circuit for the benefit of increased calculation speed in the logic circuit (Hashiguchi [0232]). Hashiguchi further teaches a diffusion prevention layer between the first semiconductor layer and the second semiconductor layer for the benefit of preventing diffusion of both metal and water (Hashiguchi [0108]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Tonegawa and Hashiguchi to include silicide on the source and drain of a transistor in the readout circuit for the benefit of increased calculation speed in the logic circuit and to include a diffusion prevention layer between the first semiconductor layer and the second semiconductor layer for the benefit of preventing diffusion of both metal and water.
Regarding Claim 3 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses the transistor is one of a reset transistor (RST), a selection transistor (SEL), and an amplification transistor (AMP) (Tonegawa [0071] and Fig. 2).
Regarding Claim 4 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi further discloses the transistor is one of a reset transistor (RST), a selection transistor (SEL), and an amplification transistor (AMP) (Tonegawa [0071] and Fig. 2).
PNG
media_image7.png
467
421
media_image7.png
Greyscale
Regarding Claim 7 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses the salicide structure is disposed between the second semiconductor layer and the third semiconductor layer (between layers 21 and 31 Tonegawa [0065-0066]).
Regarding Claim 8 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi further discloses the silicide structure is disposed between the second semiconductor layer and the third semiconductor layer (between layers 21 and 31 Tonegawa [0065-0066]).
Regarding Claim 9 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses the first member and the second member are electrically connected with a through-wiring line passing through an insulator (51 Tonegawa [0077] and Fig. 22) included in the second semiconductor layer and an insulating layer included in the first wiring structure (Tonegawa Fig. 22).
Regarding Claim 10 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi further discloses the first member and the second member are electrically connected with a through-wiring line passing through an insulator (51 Tonegawa [0077] and Fig. 22) included in the second semiconductor layer and an insulating layer included in the first wiring structure (Tonegawa Fig. 22).
Regarding Claim 13 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses the diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide (Hashiguchi [0107]).
Regarding Claim 14 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi further discloses the diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide (Hashiguchi [0107]).
Regarding Claim 19 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses at least one of a source region, a drain region, and a gate of a transistor forming the signal processing circuit includes a salicide structure (salicide formed on source and drain of logic circuit 32 Tonegawa [0066]).
Regarding Claim 20 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi further discloses at least one of a source region, a drain region, and a gate of a transistor forming the signal processing circuit includes a silicide structure (silicide formed on source and drain of logic circuit 32 Tonegawa [0066]).
Regarding Claim 21 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 19.
The combination of Tonegawa and Hashiguchi fails to explicitly disclose a metal element included in the salicide structure included in the transistor forming the readout circuit is different from a metal element included in the salicide structure included in the transistor forming the signal processing circuit.
However, the combination of Tonegawa and Hashiguchi further discloses the metal used to form the salicide can be chosen among commonly known alternatives such as cobalt or nickel (Tonegawa [0066]). Substituting art recognized equivalents for the same purpose is a prima facie case of obviousness. see MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider substituting a different metal element for the salicide in the signal processing circuit compared with the metal element for the salicide in the readout circuit.
Regarding Claim 22 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 20.
The combination of Tonegawa and Hashiguchi fails to explicitly disclose a metal element included in the silicide structure included in the transistor forming the readout circuit is different from a metal element included in the silicide structure included in the transistor forming the signal processing circuit.
However, the combination of Tonegawa and Hashiguchi further discloses the metal used to form the silicide can be chosen among commonly known alternatives such as cobalt or nickel (Tonegawa [0066]). Substituting art recognized equivalents for the same purpose is a prima facie case of obviousness. see MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider substituting a different metal element for the silicide in the signal processing circuit compared with the metal element for the silicide in the readout circuit.
Regarding Claim 23 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi further discloses at least any one of: an optical device adapted to the photoelectric conversion apparatus, a control device configured to control the photoelectric conversion apparatus, a processing device configured to process a signal output from the photoelectric conversion apparatus, a display device configured to display information obtained by the photoelectric conversion apparatus, a storage device configured to store information obtained by the photoelectric conversion apparatus, and a mechanical device configured to operate based on information obtained by the photoelectric conversion apparatus (CCU 11201 processes the information obtained by the photoelectric conversion apparatus Tonegawa [0200] and Fig. 26).
PNG
media_image8.png
678
569
media_image8.png
Greyscale
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tonegawa et al (US 20250221070 A1, hereinafter “Tonegawa”), in view of Hashiguchi (US 20250072150 A1, hereinafter “Hashiguchi”), and further in view of Chen (US 20210217798 A1, hereinafter “Chen”).
Regarding Claim 5 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi fails to disclose a gate of the transistor includes the salicide structure.
However, Chen discloses a gate of the transistor includes the salicide structure (SAC_GL Chen [0033] and Fig. 9).
Chen discloses an analogous CMOS gate construction to the photoelectric conversion circuit transistors in Tonegawa. Chen teaches that silicide is formed on contacts, such as the gate, to reduce contact resistance (Chen [0004]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form silicide on the gate of a transistor to reduce contact resistance.
Regarding Claim 6 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi fails to disclose a gate of the transistor includes the silicide structure, and the silicide structure included in the gate is in contact with the insulating film included in the second wiring structure.
However, Chen discloses a gate of the transistor includes the silicide structure (SAC_GL Chen [0033] and Fig. 9), and the silicide structure included in the gate is in contact with the insulating film included in the second wiring structure (112 Chen [0035] and Fig. 9).
Chen discloses an analogous CMOS gate construction to the photoelectric conversion circuit transistors in Tonegawa. Chen teaches that silicide is formed on contacts, such as the gate, to reduce contact resistance (Chen [0004]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form silicide on the gate of a transistor to reduce contact resistance.
PNG
media_image9.png
465
377
media_image9.png
Greyscale
Claims 11, 12, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tonegawa et al (US 20250221070 A1, hereinafter “Tonegawa”), in view of Hashiguchi (US 20250072150 A1, hereinafter “Hashiguchi”), and further in view of Nakazawa (US 20220271070 A1, hereinafter “Nakazawa”).
Regarding Claim 11 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 1.
The combination of Tonegawa and Hashiguchi fails to disclose another diffusion prevention layer to prevent diffusion of metal included in the salicide structure is disposed between the second semiconductor layer and the second wiring structure.
However, Nakazawa discloses another diffusion prevention layer is disposed between the second semiconductor layer and the second wiring structure (passivation film 221 Nakazawa [0401] and Fig. 71).
Nakazawa discloses a similar photoelectric conversion apparatus to Tonegawa. Nakazawa teaches including a diffusion prevention layer between the second semiconductor layer and the second wiring structure for the benefit of suppressing leakage current (Nakazawa [0401]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Tonegawa and Nakazawa to include the diffusion prevention layer between the second semiconductor layer and the second wiring structure for the benefit of suppressing leakage current.
Regarding Claim 12 – Tonegawa modified by Hashiguchi discloses all the limitations of claim 2.
The combination of Tonegawa and Hashiguchi fails to disclose another diffusion prevention layer to prevent diffusion of metal included in the silicide structure is disposed between the second semiconductor layer and the second wiring structure.
However, Nakazawa discloses another diffusion prevention layer is disposed between the second semiconductor layer and the second wiring structure (passivation film 221 Nakazawa [0401] and Fig. 71).
Nakazawa discloses a similar photoelectric conversion apparatus to Tonegawa. Nakazawa teaches including a diffusion prevention layer between the second semiconductor layer and the second wiring structure for the benefit of suppressing leakage current (Nakazawa [0401]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Tonegawa and Nakazawa to include the diffusion prevention layer between the second semiconductor layer and the second wiring structure for the benefit of suppressing leakage current.
PNG
media_image10.png
481
631
media_image10.png
Greyscale
Regarding Claim 15 – Tonegawa modified by Hashiguchi, and further modified by Nakazawa, discloses all the limitations of claim 11.
The combination of Tonegawa, Hashiguchi, and Nakazawa further discloses the another diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide (Hashiguchi [0107]).
Regarding Claim 16 – Tonegawa modified by Hashiguchi, and further modified by Nakazawa, discloses all the limitations of claim 12.
The combination of Tonegawa, Hashiguchi, and Nakazawa further discloses the another diffusion prevention layer includes any one of silicon nitride, silicon oxynitride, and silicon carbide (Hashiguchi [0107]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898