DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claim 14 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. If Applicant intends any particular total area of the first portion of the first control circuit and the second control circuit with respect to the total area of the second portion of the first control circuit, the first memory cell array and the second memory cell array, it should be clearly recited.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (11,342,352).
Re claim 1, Chen et al. disclose a first substrate (401) with a first circuit layer (410) on a front surface, the first circuit layer (410) including a CMOS circuit (412) (Fig. 5); and a second substrate (101) (Fig. 4) having a front surface facing the front surface of the first substrate, the second substrate (101) being provided with a second circuit layer (220) on the front surface contacting the first circuit layer (410), and the second circuit layer (220) including a memory circuit (220 ~ NAND) and transistors (112) of a silicon-on-insulator (SOI) structure (101 ~ Col. 6, lines 15-18).
Re claim 13, Chen et al. disclose wherein the second substrate is provided with a plurality of memory cell arrays (NAND), and the plurality of memory cell arrays includes a first memory cell array with a memory circuit connected to the CMOS circuit (412) via one of the transistors of the SOI structure and a second memory cell array with a memory circuit connected to the CMOS circuit by none of the transistors of the SOI structure (Col. 5, lines 45-60).
Re claim 17, Chen et al. disclose wherein the CMOS circuit is not above the second substrate (Fig. 6).
Re claim 18, Chen et al. disclose wherein the first circuit layer (410) includes a second conductor layer (430), the second circuit layer (220) includes a third conductor layer (338) in contact with the second conductor layer, the second conductor layer and the third conductor layer are connected in series between the transistors and the CMOS circuit, the second conductor layer has a reverse taper shape, and the third conductor layer has a taper shape (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. as applied to claims 1, 13, 17 and 18 above, and further in view of the following comments.
Re claim 16, Chen et al. disclose does not clearly disclose wherein the transistors are high-voltage transistors.
However, using high-voltage transistors in memory devices are well known in the art before the effective filing date of the present invention. Therefore, it would have been obvious to one of ordinary skill in the art to use the known high-voltage transistors for its own intended purpose.
Allowable Subject Matter
Claims 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pending the correction of issues outlined in the rejection above, the following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest the following in combination the remaining limitations called for in each claim:
further comprising: a first insulator layer on a back surface of the second substrate, wherein the second substrate includes: a first insulating member in contact with the first insulator layer and dividing the second substrate into regions including well regions in each of which a transistor is formed; the second circuit layer includes: a second insulator layer on the front surface of the second substrate, and a gate electrode of one of the transistors facing one of the well regions with the second insulator layer being between the gate electrode and the one of the well regions; the transistors being separated into islands by the first insulating member, as recited in claim 2;
wherein transistors in the CMOS circuit are different from the island-shaped insulating SOI structure of the transistors in the well regions of the second substrate, as recited in claim 3;
wherein the second circuit layer further includes: a plurality of contacts extending in a first direction and having lower surfaces at the same height, the plurality of contacts including a contact coupled to the one of the well regions and a contact coupled to the gate electrode, as recited in claim 4;
wherein the second substrate includes a first impurity diffusion region including an N-type impurity, the first impurity diffusion region extending from the front surface to the back surface of the second substrate, the second circuit layer further includes: a first semiconductor layer below the first impurity diffusion region in the first direction, a second semiconductor layer under the first semiconductor layer in the first direction, a plurality of word lines stacked in the first direction below the second semiconductor layer, and a memory pillar extending in the first direction and intersecting the plurality of word lines to form memory cells, the first semiconductor layer and the second semiconductor layer function a source line in the memory circuit, and the thickness of the second semiconductor layer along the first direction is substantially equal to the thickness of the gate electrode along the first direction, as in claim 5;
wherein the height of a lower surface of the second semiconductor layer is substantially the same as the height of a lower surface of the gate electrode, as recited in claim 6;
wherein each of the plurality of word lines is electrically connected to the CMOS circuit via one of the transistors of the second circuit layer, as recited in claim 7;
wherein the second circuit layer further includes a bit line extending in a second direction intersecting with the first direction, the bit line being below the plurality of word lines in the first direction and electrically connected to the memory pillar, and the bit line is also being electrically connected to the CMOS circuit via at least one of the transistors of the second circuit layer, as recited in claim 8;
further comprising: a first conductor layer on the back surface of the second substrate, wherein the second substrate includes a second impurity diffusion region including an N-type impurity from the front surface to the back surface of the second substrate, and the first conductor layer is electrically connected to the CMOS circuit through the second impurity diffusion region, as recited in claim 9;
wherein the first conductor layer is used to supply a power supply voltage to the CMOS circuit, as recited in claim 10;
wherein the second impurity diffusion region is insulated and spaced from the first impurity diffusion region, as recited in claim 11;
wherein the memory pillar includes a third semiconductor layer extending in the first direction, and the first semiconductor layer is in contact with the third semiconductor layer via a side surface of the memory pillar, as recited in claim 12.
Claims 14 and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance: there is no disclosure in the prior art of “wherein the second substrate includes: a first impurity diffusion region including N-type impurities, the first impurity diffusion region extending from the front surface to a back surface of the second substrate, and a well region insulated and spaced from the first impurity diffusion region, the second circuit layer includes: a first semiconductor layer below the first impurity diffusion region, a second semiconductor layer under the first semiconductor layer; …a gate electrode of the first-type transistor facing the well region, the well region functioning as an active region of the first-type transistor, the first-type transistor being different from the memory cell transistor, the first impurity diffusion region, the first semiconductor layer, and the second semiconductor layer function as a source line in the memory circuit, the well region is at a position corresponding to the first impurity diffusion region in the first direction, and the gate electrode is at a position corresponding to the second semiconductor layer in the first direction.
Claims 20 is also allowed as they depend from an allowed base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2017/0008760 A1, US 2018/0350785 A1, US 2024/0196631, US 2022/0359441 disclose a similar configuration for a memory device with a CMOS circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM.
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 January 29, 2026