DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 8, 2026.
Note from the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11, 13-14 are rejected under 35 U.S.C. 103 as obvious over Shin et al. (US 20210057538 A1), hereinafter referred to as “Shin”, in view of Guler et al. (US 20220399335 A1), hereinafter referred to as “Guler”, further in view of Hsieh et al. (US 20230163194 A1), hereinafter referred to as “Hsieh”.
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Regarding claim 1, Shin discloses a semiconductor structure (Shin fig. 1A and c.f. Shin fig. 1C; see Shin [0040]: Shin discloses a three-dimensional transistor device having structure comprising semiconductor material; see Shin [0042]: the semiconductor device of fig. 1C is substantially the same as the device of fig. 1C (especially in regard to the contact structures) except for the disclosed differences relating to the channel pattern and gate electrode) comprising:
a gate structure (see Shin fig. 1C and [0039]; second gate contact GCT2 is in contact with gate electrode GE, and, together, they constitute a gate structure); and
a dielectric cap layer (Shin fig. 1C, GC; see [0028]).
Shin fails to disclose said semiconductor structure comprising: a gate structure with a first portion having a first top surface and a second portion having a second top surface, the first top surface being above the second top surface; a dielectric cap layer on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer; and a gate contact being above and substantially aligned with the first portion of the gate structure.
Guler discloses an integrated circuit structure (Guler fig. 3B, 370; see [0046]) for a gate-all-around transistor (see Guler [0063]; note that Guler fig. 3B shows the gate portion of a gate-all-around transistor) comprising a gate electrode (Guler fig. 3B, 378 and 382; see [0046]: since trench contact via 382 is coupled to gate electrode 378, they can be both be taken as one monolithic gate structure) surrounding at least one stack of nanostructures (see Guler fig. 3B and [0046]; note that nanowires 376 are arranged in a stack). Guler thus discloses a semiconductor structure (Guler fig. 3B, 370; see [0047] and note that integrated circuit structure 370 is partly composed of semiconductor material) comprising: a gate structure (Guler fig. 3B, 378 and 382) with a first portion (Guler fig. 3B, 382) having a first top surface (see Guler fig. 3B; the first top surface of trench contact via 382 being the horizontal surface opposite gate electrode 378) and a second portion (Guler fig. 3B, 378) having a second top surface (the second top surface of gate electrode 378 is the horizontal surface below insulating cap 380), the first top surface being above the second top surface (see Guler fig. 3B; the first top surface of the trench contact via 382 is above the second top surface of gate electrode 378); and
a dielectric cap layer (Guler fig. 3B, 380; see Guler [0046]) on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer (see Guler fig. 3B; insulating cap 380 is on top of gate electrode 378, and trench contact via 382 is embedded in insulating cap 380).
The gate structure and dielectric cap layer of Guler are herein incorporated as the gate structure and dielectric cap layer of Shin, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Shin with the gate structure as taught in Guler to reduce fabrication time by forming the gate structure in one deposition step (since the gate structure of Guler is made of a single material (see Guler [0057] and [0059]), it can be fabricated in one deposition step, whereas the gate structure of Shin is fabricated in two distinct process steps (see Shin [0046] and [0054]; [0046] confirms that Shin fig. 8B shows a process stage during fabrication of the device of Shin fig. 1A, and [0054] confirms that second gate contact plug GCT2 is fabricated in a distinct step after the formation of the gate electrode GE));
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the gate structure as taught by Shin (Shin fig. 1C, GCT2 and GE) with the gate structure as taught by Guler (Guler fig. 3B, 378 and 382) to obtain predictable results (i.e. reduced fabrication time);
further note that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure taught in Shin with the dielectric cap layer as taught in Guler in order to protect said second portion of said gate structure (Guler fig. 3B, 378) from environmental damage (moisture, contamination, etc.);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the gate capping layer as taught by Shin (Shin fig. 1C, GC) with the insulating cap as taught by Guler (Guler fig. 3B, 380) to obtain predictable results (i.e. protection from environmental damage).
Hsieh discloses techniques for forming contact plugs for transistor devices (see Hsieh [0010]; note that the techniques disclosed in Hsieh can be applied to Gate-all-around transistors), wherein substantially aligned metallic contact plugs (Hsieh fig. 23, 82 and 90; see Hsieh [0053]; also see Hsieh [0055] and note that the embodiment of Hsieh fig. 23 is similar to the embodiment of fig. 22A except for the disclosed differences) are coupled to a gate electrode (Hsieh fig. 23, 54; see Hsieh [0028]) of a FinFET device (Hsieh fig. 23, 92; see Hsieh [0055]). Hsieh thus discloses a semiconductor structure (see Hsieh [0012] and note that substrate 20 is a semiconductor substrate) comprising a gate contact (Hsieh fig. 23, 90) being above and substantially aligned with a first portion (Hsieh fig. 23, 82; note that gate contact plug 90 both contacts gate contact plug 82 (see Hsieh [0053]) and is substantially aligned with gate contact plug 82) of a gate structure (see Hsieh fig. 23 and c.f. fig. 22B; the gate structure comprises gate electrode 54 (i.e. second (lower) portion) and gate contact plug 82 (i.e. first (raised) portion); see Hsieh [0053]-[0055] and note that the embodiment of fig. 22B is similar to the embodiment of fig. 23 except for the disclosed differences).
The gate contact of Hsieh is incorporated with the combined structure of Shin and Guler, wherein the combination discloses a semiconductor structure (Shin fig. 1A) comprising:
a gate structure (Guler fig. 3B, 378 and 382) with a first portion (Guler fig. 3B, 382) having a first top surface (see Guler fig. 3B) and a second portion (Guler fig. 3B, 378) having a second top surface (see Guler fig. 3B), the first top surface being above the second top surface (see Guler fig. 3B);
a dielectric cap layer (Guler fig. 3B, 380) on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer (see Guler fig. 3B);
and a gate contact (Hsieh fig. 23, 90) being above and substantially aligned with the first portion of the gate structure (in the combined structure, the gate contact plug 90 of Hsieh is above and substantially aligned with the first portion of the gate structure (i.e. Guler fig. 3B, 382; see annotated Shin fig. 1C above); note also that, in the combined structure, said gate contact is disposed above said first (raised) portion of the gate structure, wherein the top surface of said gate contact is coplanar with the top surface of the upper insulating layer of Shin (Shin fig. 1C, IL)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Shin and Guler with the gate contact as taught in Hsieh in order to reduce wasted material by aligning the gate contact with the first (raised) portion of the gate structure.
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Regarding claim 2, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 1, further comprising a source/drain contact (Shin fig. 1C, CP; see Shin [0032]) adjacent to the gate structure (in the combined structure, the gate structure comprises the gate structure of Guler (Guler fig. 3B, 378 and 382) substituted for the gate electrode (Shin fig. 1C, GE) and the second gate contact plug (Shin fig. 1C, GCT2) of the device in Shin; the source/drain contact pad (Shin fig. 1C, CP; note that the indicated contact pad is the source/drain contact) is adjacent to this gate structure), wherein the source/drain contact has a top surface that is below the first top surface of the first portion of the gate structure (see annotated Shin fig. 1C above; the top surface of contact pad CP is below the top surface the gate electrode GE (which indicates the location of the second (lower) portion of the gate structure); therefore, in the combined structure, the top surface of the source/drain contact is below the top surface of the first (raised) portion of the gate structure (Guler fig. 3B, 382)).
Regarding claim 3, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 2, further comprising a sidewall spacer (Shin fig. 1C, GS; see Shin [0029]) at a sidewall of the gate structure (in the combined structure, the gate structure comprises the gate structure of Guler (Guler fig. 3B, 378 and 382) substituted for the gate electrode (Shin fig. 1C, GE) and the second gate contact plug (Shin fig. 1C, GCT2) of the device in Shin; c.f. Shin fig. 1C and note that gate spacer GS is located at a sidewall of said gate structure) and in between the gate structure and the source/drain contact (see Shin fig. 1C and [0032]; gate spacer GS is located in between the source/drain contact pad CP and said gate structure), wherein a height of the sidewall spacer is greater than a height of the source/drain contact (see Shin fig. 1C; the height of gate spacer GS is greater than the height of contact pad CP as shown).
Regarding claim 4, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 3, wherein an upper portion of the sidewall spacer (Shin fig. 1C, GS) above the source/drain contact (Shin fig. 1C, CP) has a non-uniform thickness (see Shin fig. 1C; the thickness of gate spacer GS above contact pad CP is non-uniform (i.e. tapered)).
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Regarding claim 5, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 3, further comprising a via contact (Shin fig. 1C, SCT; see Shin [0037] and c.f. Shin fig. 1A; see Shin [0010] and note that fig. 1C shows cross-sections of the device depicted in fig. 1A) contacting the top surface of the source/drain contact (Shin fig. 1C, CP; see Shin [0037]; source/drain contact plug SCT contacts the top surface of contact pad CP), wherein a top surface of the via contact is coplanar with a top surface of the gate contact (Hsieh fig. 22B, 90; see annotated Shin fig. 1C above and note that, in the combined structure, the top surface of source/drain contact plug SCT is coplanar with the gate contact plug incorporated from Hsieh).
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Regarding claim 6, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 5, wherein the gate structure (in the combined structure, the gate structure comprises the gate structure of Guler (Guler fig. 3B, 378 and 382) substituted for the gate electrode (Shin fig. 1C, GE) and the second gate contact plug (Shin fig. 1C, GCT2) of the device in Shin) surrounds a set of nanosheets (Shin fig. 1C, CH; see Shin [0041]; in the combined structure, the second (lower) portion of the gate structure surrounds the channel pattern CH), and the source/drain contact (Shin fig. 1C, CP) is above an epitaxial source/drain region (Shin fig. 1C, SD; see Shin [0030]; contact plug CP is above source/drain pattern SD as shown) formed at an end of the set of nanosheets (Shin fig. 1C, CH; source/drain pattern SD is formed at the end of channel pattern CH as shown).
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Regarding claim 7, Shin, Guler, and Hsieh, disclose the semiconductor structure of claim 5, wherein cross-sections of the via contact (Shin fig. 1A and fig. 1C, SCT) and the gate contact (Hsieh fig. 22B, 90; in the combined structure, the gate contact plug incorporated from Hsieh is located at the location of second gate contact plug GCT2 as depicted in Shin fig. 1A and fig. 1C), made perpendicular to a length direction of the gate structure, do not overlap with each other (see Shin fig. 1A; cross-sections of source/drain contact plug SCT and of gate contact plug GCT2 (which indicates the location of the gate contact in the combined structure) made perpendicular to the third gate patten GP3 (which indicates the location of the gate structure in the combined structure) do not overlap with each other; see Shin [0010] and note that fig. 1C shows cross-sections of the device depicted in fig. 1A).
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Regarding claim 8, Shin discloses a semiconductor device (Shin fig. 1A and c.f. Shin fig. 1C; see Shin [0040]: Shin discloses a three-dimensional transistor device; see Shin [0042]: the semiconductor device of fig. 1C is substantially the same as the device of fig. 1C (especially in regard to the contact structures) except for the disclosed differences relating to the channel pattern and gate electrode) comprising:
a set of nanosheets (Shin fig. 1C, CH; see Shin [0041]);
a gate structure (see Shin fig. 1C and [0039]; second gate contact GCT2 is in contact with gate electrode GE, and, together, they constitute a gate structure) surrounding the set of nanosheets (see Shin fig. 1C and [0042]: gate electrode GE surrounds channel pattern CH);
and a dielectric cap layer (Shin fig. 1C, GC; see [0028]).
Shin fails to disclose the gate structure having a first portion of a first height and a second portion of a second height, the first height being greater than the second height;
a dielectric cap layer on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer;
and a gate contact being above and substantially aligned with the first portion of the gate structure.
Guler discloses an integrated circuit device (Guler fig. 3B, 370; see [0046]) for a gate-all-around transistor (see Guler [0063]; note that Guler fig. 3B shows the gate portion of a gate-all-around transistor) comprising a gate electrode (Guler fig. 3B, 378 and 382; see [0046]: since trench contact via 382 is coupled to gate electrode 378, they can be both be taken as one monolithic gate structure) surrounding at least one stack of nanostructures (see Guler fig. 3B and [0046]; note that nanowires 376 are arranged in a stack). Guler thus discloses a semiconductor device (Guler fig. 3B, 370; see [0047] and note that integrated circuit element 370 is partly composed of semiconductor material) wherein a gate structure (Guler fig. 3B, 378 and 382) has a first portion (Guler fig. 3B, 382) of a first height (see Guler fig. 3B) and a second portion (Guler fig. 3B, 378) of a second height (see Guler fig. 3B), the first height being greater than the second height (see Guler fig. 3B: the first height of trench contact via 382 is greater than the second height of gate electrode 378); and
a dielectric cap layer (Guler fig. 3B, 380; see Guler [0046]) on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer (see Guler fig. 3B; insulating cap 380 is on top of gate electrode 378, and trench contact via 382 is embedded in insulating cap 380).
The gate structure and dielectric cap layer of Guler are herein incorporated as the gate structure and dielectric cap layer for the device of Shin, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Shin with the gate structure as taught in Guler to reduce fabrication time by forming the gate structure in one deposition step (since the gate structure of Guler is made of a single material (see Guler [0057] and [0059]), it can be fabricated in one deposition step, whereas the gate structure of Shin is fabricated in two distinct process steps (see Shin [0046] and [0054]; [0046] confirms that Shin fig. 8B shows a process stage during fabrication of the device of Shin fig. 1A, and [0054] confirms that second gate contact plug GCT2 is fabricated in a distinct step after the formation of the gate electrode GE));
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the gate structure as taught by Shin (Shin fig. 1C, GCT2 and GE) with the gate structure as taught by Guler (Guler fig. 3B, 378 and 382) to obtain predictable results (i.e. reduced fabrication time);
further note that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Shin with the dielectric cap layer as taught in Guler in order to protect said second portion of said gate structure (Guler fig. 3B, 378) from environmental damage (moisture, contamination, etc.);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the gate capping layer as taught by Shin (Shin fig. 1C, GC) with the insulating cap as taught by Guler (Guler fig. 3B, 380) to obtain predictable results (i.e. protection from environmental damage).
Hsieh discloses techniques for forming contact plugs for transistor devices (see Hsieh [0010]; note that the techniques disclosed in Hsieh can be applied to Gate-all-around transistors), wherein substantially aligned metallic contact plugs (Hsieh fig. 23, 82 and 90; see Hsieh [0053]; also see Hsieh [0055] and note that the embodiment of Hsieh fig. 23 is similar to the embodiment of fig. 22A except for the disclosed differences) are coupled to a gate electrode (Hsieh fig. 23, 54; see Hsieh [0028]) of a FinFET device (Hsieh fig. 23, 92; see Hsieh [0055]). Hsieh thus discloses a semiconductor structure (see Hsieh [0012] and note that substrate 20 is a semiconductor substrate) comprising a gate contact (Hsieh fig. 23, 90) being above and substantially aligned with a first portion (Hsieh fig. 23, 82; note that gate contact plug 90 both contacts gate contact plug 82 (see Hsieh [0053]) and is substantially aligned with gate contact plug 82) of a gate structure (see Hsieh fig. 23 and c.f. fig. 22B; the gate structure comprises gate electrode 54 (i.e. second (lower) portion) and gate contact plug 82 (i.e. first (raised) portion); see Hsieh [0053]-[0055] and note that the embodiment of fig. 22B is similar to the embodiment of fig. 23 except for the disclosed differences).
The gate contact of Hsieh is incorporated with the combined device of Shin and Guler, wherein the combination discloses a semiconductor device (Shin fig. 1A) comprising:
a set of nanosheets (Shin fig. 1C, CH; see Shin [0041]);
a gate structure (Guler fig. 3B, 378 and 382) surrounding the set of nanosheets;
the gate structure having a first portion (Guler fig. 3B, 382) of a first height (see Guler fig. 3B) and a second portion (Guler fig. 3B, 378) of a second height (see Guler fig. 3B), the first height being greater than the second height (see Guler fig. 3B);
a dielectric cap layer (Guler fig. 3B, 380) on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer (see Guler fig. 3B);
and a gate contact (Hsieh fig. 23, 90) being above and substantially aligned with the first portion of the gate structure (in the combined device, the gate contact plug 90 of Hsieh is above and substantially aligned with the first portion of the gate structure (i.e. Guler fig. 3B, 382; see annotated Shin fig. 1C above); note also that, in the combined device, said gate contact is disposed above said first (raised) portion of the gate structure, wherein the top surface of said gate contact is coplanar with the top surface of the upper insulating layer of Shin (Shin fig. 1C, IL)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Shin and Guler with the gate contact as taught in Hsieh in order to reduce wasted material by aligning the gate contact with the first (raised) portion of the gate structure.
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Regarding claim 9, Shin, Guler, and Hsieh, disclose the semiconductor device of claim 8, further comprising a first and a second epitaxial source/drain region (Shin fig. 1C, SD) at a first and a second end of the set of nanosheets (Shin fig. 1C, CH; the indicated first and second source/drain regions SD are located at a first and second end of channel pattern CH).
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Regarding claim 10, Shin, Guler, and Hsieh, disclose the semiconductor device of claim 9, further comprising a first and a second source/drain contact (Shin fig. 1C, CP) above the first and the second epitaxial source/drain region (Shin fig. 1C, SD) respectively and the first and the second source/drain contact being adjacent to the gate structure (in the combined device, the gate structure comprises the gate structure of Guler (Guler fig. 3B, 378 and 382) substituted for the gate electrode (Shin fig. 1C, GE) and the second gate contact plug (Shin fig. 1C, GCT2) of the device in Shin;
the indicated source/drain contact pads CP are located on either side of and adjacent to said gate structure (the location of said gate structure being indicated by third gate pattern GP3 (c.f. Shin fig. 1A)), wherein at least a top surface of the first source/drain contact is below a top surface of the first portion of the gate structure (see annotated Shin fig. 1C above; the top surface of indicated first source/drain contact is below the top surface of the gate electrode GE (which indicates the location of the second (lower) portion of the gate structure); therefore, in the combined device, the top surface of the indicated first source/drain contact is below the top surface of the first (raised) portion of the gate structure (Guler fig. 3B, 382)).
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Regarding claim 11, Shin, Guler, and Hsieh, disclose the semiconductor device of claim 10, further comprising a sidewall spacer (Shin fig. 1C, GS; see Shin [0029]) between the gate structure (in the combined device, the gate structure comprises the gate structure of Guler (Guler fig. 3B, 378 and 382) substituted for the gate electrode (Shin fig. 1C, GE) and the second gate contact plug (Shin fig. 1C, GCT2) of the device in Shin; third gate pattern GP3 as shown in Shin fig. 1C indicates the location of said gate structure) and the first source/drain contact (see annotated fig. 1C above; the indicated sidewall spacer (i.e. gate spacer GS) is located between the indicated first source/drain contact and the third gate pattern (indicating the location of the gate structure) as shown), wherein the first source/drain contact has a height that is smaller than a height of the sidewall spacer (see annotated Shin fig. 1C above; the indicated first source/drain contact has a height that is smaller than that of the indicated sidewall spacer).
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Regarding claim 13, Shin, Guler, and Hsieh, disclose the semiconductor device of claim 11, further comprising a via contact (Shin fig. 1C, SCT; see Shin [0037] and c.f. Shin fig. 1A; see Shin [0010] and note that fig. 1C shows cross-sections of the device depicted in fig. 1A) contacting the top surface of the first source/drain contact (see annotated Shin fig. 1C above and Shin [0037]; source/drain contact plug SCT contacts the top surface of the indicated first source/drain region (i.e. contact pad CP)), wherein a top surface of the via contact is coplanar with a top surface of the gate contact (Hsieh fig. 22B, 90; see Shin fig. 1C and note that, in the combined device, the top surface of source/drain contact plug SCT is coplanar with the gate contact plug incorporated from Hsieh).
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Regarding claim 14, Shin, Guler, and Hsieh the semiconductor device of claim 13, wherein the via contact (Shin fig. 1A and fig. 1C, SCT; see Shin [0037]) and the gate contact (Hsieh fig. 22B, 90; see Shin fig. 1A and fig. 1C; note that, in the combined device, the location of the gate contact corresponds with the location of the second gate contact plug GCT2 as shown) have different offsets from a longitudinal edge of the set of nanosheets (Shin fig. 1C, CH; see Shin fig. 1A and note that Shin [0010] confirms that fig. 1C depicts various cross-sections of the device shown in fig. 1A; second gate contact plug GCT2 (which indicates the location of said gate contact) has a different offset from a longitudinal edge of active fin AF (i.e. the top edge of active fin AF as shown in Shin fig. 1A) than the offset of the indicated via contact (i.e. SCT) from that same longitudinal edge of active fin AF; see Shin [0041] and note that channel pattern (i.e. nanosheets) is disposed on the active fin AF).
Claim 12 is rejected under 35 U.S.C. 103 as obvious over Shin, in view of Guler, further in view of Hsieh, further in view of Wei et al. (US 20230052975 A1), hereinafter referred to as “Wei”
Shin, Guler, and Hsieh, disclose the semiconductor device of claim 11, wherein a lower portion of the sidewall spacer (Shin fig. 1C, GS; see Shin [0029]) has a uniform thickness (see Shin fig. 1C).
Shin, Guler, and Hsieh fail to disclose wherein a lower portion of the sidewall spacer directly between the first source/drain region and the gate structure has a uniform thickness.
Wei discloses a gate-all-around transistor (see Wei fig. 12A, [0058], and [0062]; also see Wei [0019]) comprising a first source/drain region (Wei fig. 12A, 1102B) adjacent to a gate structure (Wei fig. 12A, 1204; see Wei [0060]) with a sidewall spacer (Wei fig. 12B, 1002; see Wei [0056]) therebetween, wherein a lower portion of the sidewall spacer directly between the first source/drain region and the gate structure has a uniform thickness (see Wei fig. 12A; the thickness of a lower portion of dielectric layer 1002 between first source/drain region 1102b and gate 1204 is uniform).
The first source/drain region of Wei is incorporated as the first source/drain region in the combined device of Shin, Guler, and Hsieh, wherein a top portion of the first source/drain region is directly adjacent to the sidewall spacer (Shin fig. 1C, GS) and wherein a lower portion of the sidewall spacer directly between the first source/drain region and the gate structure has a uniform thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Shin, Guler, and Hsieh with the first source/drain region of Wei in order to improve charge carrier mobility in the device (since the first source/drain region of Wei extends above the level of the bottom of the sidewall spacer, the additional source/drain material imparts compressive stress on the lower portions of the source/drain region; this additional stress improves charge carrier mobility in the device);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the first source/drain region of Shin (Shin fig. 1C, SD) with the first source/drain region of Wei to obtain predictable results (i.e. improved carrier mobility).
Conclusion
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818