Prosecution Insights
Last updated: August 18, 2026
Application No. 18/360,873

ELECTRONIC DEVICE WITH LEAD LOCK

Final Rejection §103
Filed
Jul 28, 2023
Examiner
TIVARUS, CRISTIAN ALEXANDRU
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
35 granted / 45 resolved
+9.8% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
41 currently pending
Career history
89
Total Applications
across all art units

Statute-Specific Performance

§103
58.0%
+18.0% vs TC avg
§102
25.1%
-14.9% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 45 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Amendment filed on 05/18/2026 has been entered. Claims 1-9 and 15-20, remain pending in the application. Claims 10-14 have been withdrawn in the Response to Election/Restriction filed on 12/01/2025. Applicant’s amendments have overcome each and every 112(a) rejections previously set forth in the Non-Final Office Action mailed on 12/16/2025. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 6-9, 15-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chien et al., (United States Patent Application Publication Number US 2021/0305139 A1), hereinafter referenced as Chien_139, in view of Somma et al., (United States Patent Application Publication Number, US 2019/0287880 A1) hereinafter referenced as Somma. Regarding claim 1, Chien_139 teaches an electronic device, comprising: at least one die pad (Fig.1D, element #106), inner leads (Fig.1C, part of the lead elements #108 located inside the rectangle defined by the dashed line), and outer leads (Fig.1C, part of the lead elements #108 located outside the rectangle defined by the dashed line); at least one die attached to the at least one die pad (Fig.1C, element #102), the at least one die including an active side (paragraph [0011], rows 10-12, die element #102 can be an IC chip, IC chips include active surfaces); a lead lock disposed adjacent to an inner lead (Fig.1D, element #113, paragraph [0022], rows 12-14), the lead lock having a side support disposed on one side of the inner lead and an opening between the side support and the inner lead (Fig.1D, side supports form a forklike structure and there are openings between the side supports and the adjacent inner leads); wire bonds attached from a side of the at least one die to the inner leads (Fig.1C, element #118). Chien_139 does not teach the wire bonds are attached to the active side. Somma teaches the wire bonds are attached from the active side of the at least one die (Fig.1A, wired bonds, element #46 are attached from the active side of the die, element #42, paragraph [0007], rows 7-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Somma and disclose the wire bonds are attached from the active side of the at least one die. A “die up” arrangement offers easier testing and rework accessibility, and in some cases simplifies thermal management. Chien_139 further teaches a mold compound encapsulating the at least one die, the inner leads, the lead lock, and the wire bonds (Fig.2C, element #222), wherein a bottom surface of the side support is coplanar with a bottom surface of the inner lead (paragraph [0014], rows 12-14, paragraph [0015], rows 5-6 and 11-12, lead frames are provided in two dimensional strips and openings can be produces by stamping or etching all of the metal to form openings; as a result is the mold lock supports and the lead have a coplanar bottom surface). Regarding claim 2, the combination of Chien_139 and Somma teaches the electronic device of claim 1 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 1 further comprising a cross bar integrated with a first end of the inner lead , the inner lead and the cross bar forming a T-shape (Fig.1C, inner leads have a crossbar and form a T-shape with the cross bar). Regarding claim 3, the combination of Chien_139 and Somma teaches the electronic device of claims 1 and 2 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 2, wherein the side support includes a first end and a second end, the first end connected to the cross bar (Fig.1C, each side support had a top and bottom end, top end of the side support is connected to the cross bar through the lead frame and the outer and inner lead). Regarding claim 6, the combination of Chien_139 and Somma teaches the electronic device of claim 1 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 1, wherein the side support is substantially parallel with the inner lead (Fig.1D, side supports of element #113, and the inner lead are substantial vertical). Regarding claim 7, the combination of Chien_139 and Somma teaches the electronic device of claim 1 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 1, wherein a width of the side support is less than a width of an outer lead (Fig.1D, side supports of element #113, have a horizontal width less a horizontal width of the leads). Regarding claim 8, the combination of Chien_139 and Somma teaches the electronic device of claim 1 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 1, wherein the at least one die pad is a first die pad and the at least one die is a first die, the electronic device further including a second die pad and a second die attached to the second die pad (Fig.5A and 5B show multiple dies, element #552 and #558 and dies pads, elements #506 and #507). Regarding claim 9, the combination of Chien_139 and Somma teaches the electronic device of claim 1 as set forth in the obviousness direction. Chien_139 further teaches the electronic device of claim 8, wherein the first die and the second die are attached to the first die pad and the second die pad via a die attach material (paragraph [0014], rows 13-15). Regarding claim 15, Chien_139 teaches a multi-chip integrated circuit comprising: a plurality of die pads (Fig.5A and 5B show dies pads, elements #506 and #507), inner leads, and outer leads (Fig.5A, lead frame #504 has both inner and outer leads); a plurality of dies, a die of the plurality of dies attached to a die pad of the plurality of die pads, (Fig.5A and 5B show multiple dies, element #552 and #558, attached to dies pads, elements #506 and #507), each die of the plurality of dies having an active side (paragraph [0047], rows 15-17, dies #552 and #558 are transistors, and transistors have an active surface); a lead lock disposed adjacent to an inner lead (Fig.5A, element #528 similar to element #113, paragraph [0022], rows 12-14), the lead lock having a side support disposed on one side of the inner lead and an opening between the side support and the inner lead (Fig.5A, side supports form a forklike structure and there are openings between the side supports and the adjacent inner leads); wire bonds attached from the side of each die of the plurality of dies to the inner leads (Fig.5B, elements #518, #519, #520, #521). Chien_139 does not teach the wire bonds are attached to the active side of the dies. Somma teaches the wire bonds are attached from the active side of the die (Fig.1A, wired bonds, element #46 are attached from the active side of the die, element #42, paragraph [0007], rows 7-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Somma and disclose the wire bonds are attached from the active side of the at least one die. A “die up” arrangement offers easier testing and rework accessibility, and in some cases simplifies thermal management. Chien_139 further teaches a mold compound encapsulating the plurality of dies, the inner leads, the lead lock and the wire bonds (Fig.5C, element #522), wherein a bottom surface of the side support is coplanar with a bottom surface of the inner lead (paragraph [0014], rows 12-14, and paragraph [0015], rows 5-6 and 11-12, lead frames are provided in two dimensional strips and openings can be produces by stamping or etching all of the metal to form openings; as a result is the mold lock supports and the lead have a coplanar bottom surface). Regarding claim 16, the combination of Chien_139 and Somma teaches the multi-chip integrated circuit of claim 15 as set forth in the obviousness direction. Chien_139 further teaches the multi-chip integrated circuit of claim 15, further comprising a cross bar integrated with a first end of the inner lead leads, the inner lead and the cross bar forming a T-shape (Fig.1C, inner leads have a crossbar and form a T-shape with the cross bar). Regarding claim 17, the combination of Chien_139 and Somma teaches the multi-chip integrated circuit of claims 15 and 16 as set forth in the obviousness direction. Chien_139 further teaches the multi-chip integrated circuit of claim 16, wherein the side support includes a first end and a second end, the first end connected to the cross bar (Fig.5B, each side support had a top and bottom end, bottom end of the side support is connected to the cross bar through the lead frame and the outer and inner lead). Regarding claim 20, the combination of Chien_139 and Somma teaches the multi-chip integrated circuit of claim 15 as set forth in the obviousness direction. Chien_139 further teaches the multi-chip integrated circuit of claim 15, wherein the side support is substantially parallel with the inner lead (Fig.5B, side supports of element #528, and the inner lead are substantial vertical). Allowable Subject Matter Claim 4, 5, 18 and 19 are allowed. The following is a statement of reasons for the indication of allowable subject matter. Regarding claims 4 and 18, the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the side support is partially etched in a top surface to form a recess between the first end and the second end”. Regarding claims 5 and 19, the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the second end is substantially flush with the mold compound.”. Response to Arguments Applicant’s arguments filed on 05/18/2026 have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 28, 2023
Application Filed
Dec 16, 2025
Non-Final Rejection mailed — §103
May 18, 2026
Response Filed
Jul 24, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707949
MEMORY DEVICE
3y 11m to grant Granted Aug 11, 2026
Patent 12701983
INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD
3y 11m to grant Granted Aug 04, 2026
Patent 12685162
COOLER AND SEMICONDUCTOR DEVICE
3y 10m to grant Granted Jul 14, 2026
Patent 12677688
COAXIAL INDUCTORS FABRICATED THROUGH A DRILL-LESS VIA PROCESS
4y 6m to grant Granted Jul 07, 2026
Patent 12677668
ELECTRONIC DEVICE
3y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+21.9%)
3y 5m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 45 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month