CTNF 18/361,012 CTNF 101591 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 07-29 AIA The disclosure is objected to because of the following informalities: ( Text within parentheses is either a missing or a corrected information to character(s) in bold.) [0023] “… The block criteria may specif ic (y) different tolerances for different partitions, e.g ., Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu-tao YANG et. al., (CN 114781301 A) hereinafter YANG in view of KE DING et. al. (CN 113792525 A) hereinafter DING . Regarding claim 1 YANG discloses sections a-b and d-e of claim 1. A method comprising: by a computing system: ( YANG, Contents of the Invention, “ One aspect of the present disclosure is to provide a method for generating an analog integrated circuit layout, wherein it comprises :” ) ( YANG, Specific implementation examples, “ In some embodiments, the design of the analog integrated circuit is provided by computer system such as electronic computer aided design Electronic Computer -Aided Design, ECAD) system .” ) accessing a set of circuit layer blocks (YANG, Contents of the Invention, “ receiving a plurality of component specifications for the analogue integrated circuit by processing component. The non-final layout of the analog integrated circuit is generated by processing the component partitioning the non-final layout into a plurality of sub-units ”) performing a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process ( YANG, Specific implementation examples, “ at block 106, performing one or more verification or quality control check for each sub-unit. In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification .” ) ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufactur ability. In one embodiment, the combined layout verification comprises DRC, LVS verification and/or LVL verification .” ) generating a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks ( YANG, Specific implementation examples, “ Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC ” ) Merging verified sub-units to form a layout is not any different from generating circuit layer from randomly selected circuit blocks. and utilizing the test circuit layer in support of testing the circuit manufacturing process ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufacturability .” ) YANG does not explicitly teach obtaining a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process However, DING discloses obtaining a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process ( DING, Specific implementation examples, “ In S30, the device obtains the target layout element set corresponding to the layout element set, the layout element set in the original layout data can be replaced by the target layout element set. when the layout element set is abnormal layout element set, because the abnormal layout element set and the target layout element set have the same element characteristic, and the target layout element set has pass ed the DRC check, after replacing the abnormal layout element set, That is to make the replaced target layout element set corresponding to the abnormal layout element set of the DRC check is eliminated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YANG and of DING to yield predictable result of having only the validated circuit layer blocks/sub-units in the final circuit layer leading to validation of the final circuit layout passing the DRC. Regarding claim 2 YANG and DING teach all aspects of the claim 1 as disclosed above and YANG further discloses The method of claim 1, wherein the accessed set of circuit layout blocks comprise circuit layout blocks of differing size. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) To a person having ordinary skill in the art to which the claimed invention pertains, it would be clear that components are generally of different sizes, and thus the sub-units/circuit layout blocks are of different size. Regarding claim 3 YANG and DING teach all aspects of the claim 1 as disclosed above and YANG further discloses The method of claim 1, wherein accessing the set of circuit layout blocks comprises generating the set of circuit layout blocks as random layout patterns for a circuit design. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) As the sub-units / circuit layout blocks are generated based on the component specification, the layout patterns of sub-units could only be random. Regarding claim 4 YANG and DING teach all aspects of the claim 3 as disclosed above and YANG further discloses The method of claim 3, comprising generating the set of circuit layout blocks as random layout patterns that stress the selected design rules of the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 5 YANG and DING teach all aspects of the claim 1 as disclosed above and YANG further discloses The method of claim 1, further comprising performing a chip-level DRC process on the test circuit layer that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 6 YANG and DING teach all aspects of the claim 1 as disclosed above and YANG further discloses The method of claim 1, wherein utilizing the test circuit layer comprises generating a test chip design by combining the test circuit layer with other generated test circuit layers. ( YANG, Specific implementation examples, “ In one embodiment, the combin ed layout verification comprises DRC, LVS verification and/or LVL verification. at block 112, the combin ed layout is provided to the process design kit (process design kit, PDK). For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit .” ) Regarding claim 7 YANG and DING teach all aspects of the claim 6 as disclosed above. The teachings cited for claim 6 encompass the claim 7. YANG further discloses The method of claim 6, comprising combining the test circuit layer with other generated test circuit layers that pass a chip-level DRC process that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the combin ed layout verification comprises DRC, LVS verification and/or LVL verification. at block 112, the combin ed layout is provided to the process design kit (process design kit, PDK). For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit .” ) Specifically, “ For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit.” implies that the sub-units as well as the final combined circuit layout placed in the library are available to be combined with other circuit layouts which have undergone similar process of validation such as DRC and manufacturability. Regarding claim 8 YANG teaches a-c and e-f of claim 8. A system comprising: a processor ( YANG, Specific implementation examples, “The processing component 1602 may be (several) any suitable processing component Examples processing component but not limited to a central processing unit, a microprocessor, a distributed processing system , a special integrated circuit, a graphics processing unit, a field programmable gate array or a combination thereof.” ) and a non-transitory-machine readable medium comprising instructions that, when executed by a processor, cause a computing system to ( YANG, Specific implementation examples, “ In some embodiments, the system 1600 comprises processing the component 1602 and non-transitory computer-readable storage medium 1604 (" storage component) .” ) ( YANG, Contents of the Invention, “ Another aspect of the present disclosure is to provide a simulation integrated circuit layout generating system, wherein it comprises: processing component and storage component storage is component connected to the processing and component a plurality of instructions , when being processed, component instructions cause a plurality of operations to be executed ,” ) access a set of circuit layer blocks (YANG, Contents of the Invention, “ receiving a plurality of component specifications for the analogue integrated circuit by processing component. The non-final layout of the analog integrated circuit is generated by processing the component partitioning the non-final layout into a plurality of sub-units ”) perform a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process ( YANG, Specific implementation examples, “ at block 106, performing one or more verification or quality control check for each sub-unit. In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification .” ) ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufactur ability. In one embodiment, the combined layout verification comprises DRC, LVS verification and/or LVL verification .” ) generate a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks ( YANG, Specific implementation examples, “ Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC ” ) Merging verified sub-units to form a layout is not any different from generating circuit layer from randomly selected circuit blocks. and utilize the test circuit layer in support of testing the circuit manufacturing process. ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufacturability .” ) YANG does not explicitly teach obtain a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process However, DING discloses obtain a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process ( DING, Specific implementation examples, “ In S30, the device obtains the target layout element set corresponding to the layout element set, the layout element set in the original layout data can be replaced by the target layout element set. when the layout element set is abnormal layout element set, because the abnormal layout element set and the target layout element set have the same element characteristic, and the target layout element set has pass ed the DRC check, after replacing the abnormal layout element set, That is to make the replaced target layout element set corresponding to the abnormal layout element set of the DRC check is eliminated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YANG and of DING to yield predictable result of having only the validated circuit layer blocks/sub-units in the final circuit layer leading to validation of the final circuit layout passing the DRC. Regarding claim 9 YANG and DING teach all aspects of the claim 8 as disclosed above and YANG further discloses The system of claim 8, wherein the accessed set of circuit layout blocks comprise circuit layout blocks of differing size. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) To a person having ordinary skill in the art to which the claimed invention pertains, it would be clear that components are generally of different sizes, and thus the sub-units/circuit layout blocks are of different size. Regarding claim 10 YANG and DING teach all aspects of the claim 8 as disclosed above and YANG further discloses The system of claim 8, wherein the instructions cause the computing system to access the set of circuit layout blocks by generating the set of circuit layout blocks as random layout patterns for a circuit design. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) As the sub-units / circuit layout blocks are generated based on the component specification, the layout patterns of sub-units could only be random. Regarding claim 11 YANG and DING teach all aspects of the claim 10 as disclosed above and YANG further discloses The system of claim 10, wherein the instructions cause the computing system to generate the set of circuit layout blocks as random layout patterns that stress the selected design rules of the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 12 YANG and DING teach all aspects of the claim 8 as disclosed above and YANG further discloses The system of claim 8, wherein the instructions further cause the computing system to perform a chip-level DRC process on the test circuit layer that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 13 YANG and DING teach all aspects of the claim 8 as disclosed above and YANG further discloses The system of claim 8, wherein the instructions cause the computing system to utilize the test circuit layer by generating a test chip design by combining the test circuit layer with other generated test circuit layers. ( YANG, Specific implementation examples, “ In one embodiment, the combin ed layout verification comprises DRC, LVS verification and/or LVL verification. at block 112, the combin ed layout is provided to the process design kit (process design kit, PDK). For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit .” ) Regarding claim 14 YANG and DING teach all aspects of the claim 13 as disclosed above and YANG further discloses The system of claim 13, wherein the instructions cause the computing system to combine the test circuit layer with other generated test circuit layers that pass a chip-level DRC process that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the combin ed layout verification comprises DRC, LVS verification and/or LVL verification. at block 112, the combin ed layout is provided to the process design kit (process design kit, PDK). For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit .” ) Specifically, “ For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit.” implies that the sub-units as well as the final combined circuit layout placed in the library are available to be combined with other circuit layouts which have undergone similar process of validation such as DRC and manufacturability. Regarding claim 15 YANG teaches a-b and d-e of claim 15 A non-transitory machine-readable medium comprising instruction that, when executed by a processor, cause a computing system to ( YANG, Specific implementation examples, “ In some embodiments, the system 1600 comprises processing the component 1602 and non-transitory computer-readable storage medium 1604 (" storage component) .” ) ( YANG, Contents of the Invention, “ Another aspect of the present disclosure is to provide a simulation integrated circuit layout generating system, wherein it comprises: processing component and storage component storage is component connected to the processing and component a plurality of instructions , when being processed, component instructions cause a plurality of operations to be executed ,” ) access a set of circuit layer blocks (YANG, Contents of the Invention, “ receiving a plurality of component specifications for the analogue integrated circuit by processing component. The non-final layout of the analog integrated circuit is generated by processing the component partitioning the non-final layout into a plurality of sub-units ”) perform a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process ( YANG, Specific implementation examples, “ at block 106, performing one or more verification or quality control check for each sub-unit. In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification .” ) ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufactur ability. In one embodiment, the combined layout verification comprises DRC, LVS verification and/or LVL verification .” ) generate a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks ( YANG, Specific implementation examples, “ Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC ” ) Merging verified sub-units to form a layout is not any different from generating circuit layer from randomly selected circuit blocks. and utilize the test circuit layer in support of testing the circuit manufacturing process. ( YANG, Specific implementation examples, “ At block 110, the combined layout is checked and/or tested for quality control and manufacturability .” ) YANG does not explicitly teach obtain a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process However, DING discloses obtain a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process ( DING, Specific implementation examples, “ In S30, the device obtains the target layout element set corresponding to the layout element set, the layout element set in the original layout data can be replaced by the target layout element set. when the layout element set is abnormal layout element set, because the abnormal layout element set and the target layout element set have the same element characteristic, and the target layout element set has pass ed the DRC check, after replacing the abnormal layout element set, That is to make the replaced target layout element set corresponding to the abnormal layout element set of the DRC check is eliminated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YANG and of DING to yield predictable result of having only the validated circuit layer blocks/sub-units in the final circuit layer leading to validation of the final circuit layout passing the DRC. Regarding claim 16 . YANG and DING teach all aspects of the claim 15 as disclosed above and YANG further discloses The non-transitory machine-readable medium of claim 15, wherein the accessed set of circuit layout blocks comprise circuit layout blocks of differing size. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) To a person having ordinary skill in the art to which the claimed invention pertains, it would be clear that components are generally of different sizes, and thus the sub-units/circuit layout blocks are of different size. Regarding claim 17 YANG and DING teach all aspects of the claim 15 as disclosed above and YANG further discloses The non-transitory machine-readable medium of claim 15, wherein the instructions cause the computing system to access the set of circuit layout blocks by generating the set of circuit layout blocks as random layout patterns for a circuit design. ( YANG, Specific implementation examples, “ In one embodiment, the sub-units are generated based on component specification . Each sub-unit is a smaller circuit or component of an analogue IC .” ) As the sub-units / circuit layout blocks are generated based on the component specification, the layout patterns of sub-units could only be random. Regarding claim 18 YANG and DING teach all aspects of the claim 17 as disclosed above and YANG further discloses The non-transitory machine-readable medium of claim 17, wherein the instructions cause the computing system to generate the set of circuit layout blocks as random layout patterns that stress the selected design rules of the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 19 YANG and DING teach all aspects of the claim 15 as disclosed above and YANG further discloses The non-transitory machine-readable medium of claim 15, wherein the instructions further cause the computing system to perform a chip-level DRC process on the test circuit layer that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the verification of the sub-unit comprises a design rule check (DRC), layout (LVL) verification, and/or layout schematic (LVS) verification. Once the sub-unit is verified, the sub-units are merged to form the merged layout of the analogue IC or the analogue unit (block 108). In essence, the combining sub-unit constructs or reforms the non-final layout of the analog IC. At block 110, the combined layout is checked and/or tested for quality control and manufactur ability .” ) Regarding claim 20 YANG and DING teach all aspects of the claim 15 as disclosed above and YANG further discloses The non-transitory machine-readable medium of claim 15, wherein the instructions cause the computing system to utilize the test circuit layer by generating a test chip design by combining the test circuit layer with other generated test circuit layers that pass a chip-level DRC process that applies the design rule set for the circuit manufacturing process. ( YANG, Specific implementation examples, “ In one embodiment, the combin ed layout verification comprises DRC, LVS verification and/or LVL verification. at block 112, the combin ed layout is provided to the process design kit (process design kit, PDK). For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit .” ) Specifically, “ For example, the verified sub-unit and/or the verified combin ed layout is provided to a library for storage. The program library can be accessed when designing other types of IC. At block 114, based on PDK, manufacturing integrated circuit.” implies that the sub-units as well as the final combined circuit layout placed in the library are available to be combined with other circuit layouts which have undergone similar process of validation such as DRC and manufacturability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. The examiner can normally be reached Mon-Fri: 8:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.S./Examiner, Art Unit 2851 /JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851 Application/Control Number: 18/361,012 Page 2 Art Unit: 2851 Application/Control Number: 18/361,012 Page 3 Art Unit: 2851 Application/Control Number: 18/361,012 Page 4 Art Unit: 2851 Application/Control Number: 18/361,012 Page 5 Art Unit: 2851 Application/Control Number: 18/361,012 Page 6 Art Unit: 2851 Application/Control Number: 18/361,012 Page 7 Art Unit: 2851 Application/Control Number: 18/361,012 Page 8 Art Unit: 2851 Application/Control Number: 18/361,012 Page 9 Art Unit: 2851 Application/Control Number: 18/361,012 Page 10 Art Unit: 2851 Application/Control Number: 18/361,012 Page 11 Art Unit: 2851 Application/Control Number: 18/361,012 Page 12 Art Unit: 2851 Application/Control Number: 18/361,012 Page 13 Art Unit: 2851 Application/Control Number: 18/361,012 Page 14 Art Unit: 2851 Application/Control Number: 18/361,012 Page 15 Art Unit: 2851 Application/Control Number: 18/361,012 Page 16 Art Unit: 2851 Application/Control Number: 18/361,012 Page 17 Art Unit: 2851 Application/Control Number: 18/361,012 Page 18 Art Unit: 2851 Application/Control Number: 18/361,012 Page 19 Art Unit: 2851 Application/Control Number: 18/361,012 Page 20 Art Unit: 2851 Application/Control Number: 18/361,012 Page 21 Art Unit: 2851 Application/Control Number: 18/361,012 Page 22 Art Unit: 2851 Application/Control Number: 18/361,012 Page 23 Art Unit: 2851
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