Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection based on amendment filed March 27, 2026.
Applicant argues that the redistribution substrate of Lee is not a PCB. Examiner disagrees with this argument because it was known in the art before the effective filing date that a redistribution structure is also used as a printed circuit board (PCB). See Yoon et al. (US-20230021362-A1; ¶52 Fig. 8)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6,9,16,18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190131221 A1; Lee) in view of Matsumoto (US-20180277529-A1; Matsumoto ).
Regarding claim 1, Lee discloses a data storage device, comprising: a printed circuit board (PCB) (Fig. 9, 120;¶71); a controller (Fig. 9, 112;¶84 microcontroller) mounted directly to a surface of the PCB; a memory device (Fig. 9, 111; ¶84) mounted directly to the surface of the PCB and communicatively coupled to a signal trace (Fig. 9, 122 of layer 121b;¶84) associated with the PCB, the signal trace establishing a communication path between the memory device and the controller; and a cover (Fig. 9, 160;¶93) encapsulating the controller and the memory device.
Lee is silent on a bond wire communicatively coupling the memory device to a signal trace (not shown) associated with the PCB.. and a cover encapsulating the controller, the bond wire,
Lee discloses covering the package. At issue is the bonding method.
Matsumoto discloses a memory device (Fig. 4, 12;¶29) mounted directly to the surface of a PCB (Fig. 4, 12;¶29) by a bond wire (Fig. 4, 22;¶29) coupling the memory device to a signal trace (not shown) associated with the PCB, the signal trace establishing a communication path between the memory device and the controller (Fig. 4, 11;¶29); and a cover (Fig. 4, 23;¶31) encapsulating the controller, the bond wire, and the memory device.
Before the effective filing date of the invention the technique(s) of flip-chip and wire bonding were recognized as part of the ordinary capabilities of one skilled in the art. Accordingly one of ordinary skill in the art would have been capable of applying the known technique(s) of wire bonding to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art. MPEP 2143 (I)(D)
Regarding claim 2, Lee discloses the data storage device of claim 1, further comprising one or more passive components (¶98) mounted directly to the surface of the PCB. (Fig. 9, 120;¶71)
Lee discloses the substrate comprises passive components in addition to the controller and memory. This is interpreted to mean that passive components are mounted directly to the substrate and encapsulated just as chips 111-113.
Regarding claim 3, Lee discloses the data storage device of claim 2, wherein the one or more passive components (¶98) are encapsulated by the cover.
Lee discloses the substrate comprises passive components in addition to the controller and memory. This is interpreted to mean that passive components are mounted directly to the substrate and encapsulated just as chips 111-113.
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to encapsulate the passive component to provide protection to the passive component.
Regarding claim 4, Lee discloses the data storage device of claim 2, wherein the one or more passive components are mounted directly to the surface of the PCB using a reflow soldering process.
Lee discloses the substrate comprises passive components in addition to the controller and memory. This is interpreted to mean that passive components are mounted by solder directly to the substrate and encapsulated just as chips 111-113.
The presence of process limitations, “reflow soldering process” on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 5, Lee discloses the data storage device of claim 1, wherein the controller is mounted directly to the surface of the PCB using a reflow soldering process. (product by process)
Lee discloses the substrate comprises passive components in addition to the controller and memory. This is interpreted to mean that passive components are mounted by solder directly to the substrate and encapsulated just as chips 111-113.
The presence of process limitations, “reflow soldering process” on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 6, Lee discloses the data storage device of claim 1, wherein the cover is a molding compound. (Fig. 9, 160;¶99)
Regarding claim 9, Lee discloses the data storage device of claim 1, wherein the memory device (Fig. 9, 111; ¶84) is a first memory device and wherein the data storage device further comprises a second memory device (Fig. 9, 113; ¶84) mounted directly to the surface of the PCB such that the first memory device is positioned on a first side of the controller (Fig. 9, 112;¶84 microcontroller) and the second memory device is positioned on a second side of the controller.
Regarding claim 16, Lee discloses data storage device, comprising: a printed circuit board (PCB) (Fig. 9, 120;¶71); a first storage means (Fig. 9, 111; ¶84) mounted directly to a surface of the PCB; a first communication means (Fig. 9, 115; ¶86) communicatively coupling the first storage means to a first signal means (Fig. 9, 122 of layer 121b;¶84) associated with the PCB; a second storage means (Fig. 9, 113; ¶84) mounted directly to the surface of the PCB; a second communication means (Fig. 9, 115; ¶86) communicatively coupling the second storage means to a second signal means (Fig. 9, 122 of layer 121b;¶84) associated with the PCB; a controller means (Fig. 9, 112;¶84 microcontroller) mounted directly to the surface of the PCB between the first storage means and the second storage means and being communicatively coupled to the first storage means using the first signal means and being communicatively coupled to the second storage means using the second signal means; and a covering means (Fig. 9, 160;¶93) encapsulating the first storage means, the second storage means, the first communication means, the second communication means, and the controller means.
Regarding claim 18, Lee discloses the data storage device of claim 16, further comprising one or more electronic components (Fig. 9, 111/112/113 includes several millions of components; ¶85) coupled to the surface of the PCB (Fig. 9, 120;¶71), wherein the one or more components are encapsulated by the covering means. (Fig. 9, 160;¶93)
Regarding claim 19, Lee discloses the data storage device of claim 16, wherein the controller means (Fig. 9, 112;¶84 microcontroller) is communicatively coupled to a connection means (Fig. 9, 122 of layer 121b;¶84) of the data storage device.
Regarding claim 20, Lee discloses the data storage device of claim 16, wherein the controller means (Fig. 9, 112;¶84 microcontroller) is mounted directly to the surface of the PCB (Fig. 9, 120;¶71 using a reflow soldering process.
The presence of process limitations, “reflow soldering process” on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Claim(s) 7, 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190131221 A1; Lee) in view of in view of Matsumoto (US-20180277529-A1; Matsumoto ), and further in view of Yamazaki et al. (US 20230051739 A1; Yamazaki).
Regarding claim 7, Lee discloses the data storage device of claim 1, but is silent on wherein the controller is communicatively coupled to an interface of the data storage device using another signal trace associated with the PCB.
Yamazaki discloses a data storage device comprising an interface (Fig. 47A. 60;¶496) communicatively coupled to a controller (Fig. 47A. 60;¶496) by a bus (trace) (Fig. 47A. 60;¶496) on the substrate.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine an interface with data storage device for the benefit of allowing interaction with the device from an outside source.
Regarding claim 8, Lee discloses the data storage device of claim 1, but is silent on wherein the memory device is a stack of NAND memory dies.
Yamazaki discloses a data storage device comprising a memory device is a stack of NAND memory dies. (Fig. 47A, 40 3D OS NAND; ¶504)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine NAND with the memory device for optimal storage density.
Regarding claim 17, Lee discloses the data storage device of claim 16, but is silent on wherein the first storage means and the second storage means are comprised of NAND memory dies.
Lee discloses in paragraph 84 -85 that chips 111,112,113 comprise memory and multiple elements. Lee discloses using HBMs or the like. The phrase “or the like” includes other types of memory.
Yamazaki discloses a data storage device comprising a memory device is a stack of NAND memory dies. (Fig. 47A, 40 3D OS NAND; ¶504)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine NAND with the memory device for optimal storage density.
Claim(s) 10 -13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190131221 A1; Lee) in view of in view of Matsumoto (US-20180277529-A1; Matsumoto ), and further in view of Chang et al. (US 20240297087 A1; Chang).
Regarding claim 10, Lee discloses a method for assembling a data storage device, comprising: coupling a controller (Fig. 9, 112;¶84 microcontroller) to a surface of a printed circuit board (PCB) (Fig. 9, 120;¶71); coupling one or more passive components (¶98) to the surface of the PCB;…; coupling a memory device (Fig. 9, 111; ¶84) to the surface of the PCB; electrically coupling the memory device to a signal trace (Fig. 9, 122 of layer 121b;¶84) associated with the PCB; and encapsulating (Fig. 9, 160;¶93) the controller, the one or more passive components and the memory device with a single cover.
Lee discloses the substrate comprises passive components in addition to the controller and memory. This is interpreted to mean that passive components are mounted by solder directly to the substrate and encapsulated just as chips 111-113.
Lee is silent on performing a reflow soldering process to secure the controller and the one or more passive components to the surface of the PCB.
Lee is silent on electrically coupling the memory device to a signal trace associated with the PCB using a bond wire; and encapsulating the controller, the one or more passive components, the bond wire, Lee discloses covering the package. At issue is the bonding method.
Matsumoto discloses a memory device (Fig. 4, 12;¶29) mounted directly to the surface of a PCB (Fig. 4, 12;¶29) by a bond wire (Fig. 4, 22;¶29) coupling the memory device to a signal trace (not shown) associated with the PCB, the signal trace establishing a communication path between the memory device and the controller (Fig. 4, 11;¶29); and a cover (Fig. 4, 23;¶31) encapsulating the controller, the bond wire, and the memory device.
Before the effective filing date of the invention the technique(s) of flip-chip and wire bonding were recognized as part of the ordinary capabilities of one skilled in the art. Accordingly one of ordinary skill in the art would have been capable of applying the known technique(s) of wire bonding to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art. MPEP 2143 (I)(D)
It is known in the art to reflow solder as used by Lee in order to form a strong bond between layers. However, Lee is silent on how the solder is processed.
Chang discloses a reflow process to form a solder bond. (Fig. 2B, 128; ¶79)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to reflow the solder for making a strong bond between the components and the substrate.
Regarding claim 11, Lee in view of Chang discloses the method of claim 10, wherein the signal trace (Fig. 9, 122 of layer 121b;¶84 Lee) communicatively couples the memory device (Fig. 9, 111; ¶84 Lee) to the controller. (Fig. 9, 112; ¶84 microcontroller Lee)
Regarding claim 12, Lee in view of Chang discloses the method of claim 10, wherein the single cover (Fig. 9, 160;¶93 Lee) is comprised of a molding compound.
Regarding claim 13, Lee in view of Chang discloses the method of claim 10, wherein the controller (Fig. 9, 112; ¶84 microcontroller Lee) is coupled to the surface of the PCB (Fig. 9, 120;¶71 Lee) using one or more bump pads (Fig. 9, 112P;¶86 Lee) and one or more copper (Fig. 2B, 128; ¶79 Chang) pillars. (Fig. 9, 112B;¶86 Lee)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use copper for a pillar due to its known efficacy as a conductor of electricity.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190131221 A1; Lee) in view of in view of Matsumoto (US-20180277529-A1; Matsumoto ), Chang et al. (US 20240297087 A1; Chang) and further in view of Yamazaki et al. (US 20230051739 A1; Yamazaki).
Regarding claim 14, Lee in view of Chang discloses the method of claim 10, but is silent on further comprising communicatively coupling the controller to a connection interface provided on the surface of the PCB.
Yamazaki discloses a data storage device comprising an interface (Fig. 47A. 60;¶496) communicatively coupled to a controller (Fig. 47A. 60;¶496) by a bus (trace) (Fig. 47A. 60;¶496) on the substrate.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine an interface with data storage device for the benefit of allowing interaction with the device from an outside source.
Regarding claim 15, Lee in view of Chang discloses the method of claim 10, but is silent on wherein the memory device is a stack of NAND memory dies.
Yamazaki discloses a data storage device comprising a memory device is a stack of NAND memory dies. (Fig. 47A, 40 3D OS NAND; ¶504)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine NAND with the memory device for optimal storage density.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899