DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 7, 2026 has been entered.
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Claim 16 is written broadly enough that the bond wire does not have to be couple to a trace. A signal means can be a pads and or various wiring configurations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto (US-20180277529-A1; Matsumoto).
Regarding claim 16, Matsumoto discloses a data storage device, comprising: a printed circuit board (PCB) (Fig. 4, 21; ¶30);a first storage means (Fig. 4, 12a; ¶33) mounted directly to a surface of the PCB; a first communication means (Fig. 4, 22; ¶34) having a first end coupled to the first storage means and a second end coupled to a first signal means (pad and wiring network of 21 not shown) associated with the PCB; a second storage means (Fig. 4, 12b; ¶33) mounted directly to the surface of the PCB; a second communication means (Fig. 4, 22; ¶34) having a first end coupled to the second storage means and a second end coupled to a second signal means (pad and wiring network of 21 not shown) associated with the PCB; a controller means (Fig. 4, 11; ¶34) mounted directly to the surface of the PCB between the first storage means and the second storage means, wherein the first signal means (pad and wiring network of 21 not shown) establishes a communication path between the first storage means (Fig. 4, 12a; ¶33) and the controller means, wherein the second signal means (pad and wiring network of 21 not shown) establishes a communication path between the second storage means (Fig. 4, 12b; ¶33) and the controller means, and wherein the controller means, the first storage means, andstorage means, the second storage means, the first communication means, the second communication means, and the controller means.
The package of Matsumoto would be inoperable without at least conductive pads connected to surface or internal wiring providing electric communication between the controller and memory stacks.
Regarding claim 18, Matsumoto discloses the data storage device of claim 16, further comprising one or more electronic components (Fig. 4, 13; ¶34) coupled to the surface of the PCB (Fig. 4, 21; ¶30), wherein the one or more (electronic) components are encapsulated by the covering means. (Fig. 4, 23; ¶28)
Regarding claim 19, Matsumoto discloses the data storage device of claim 16, wherein the controller means (Fig. 4, 11; ¶34) is communicatively coupled (by a pad and wiring network of 21 not shown) to a connection means (pad and wiring network of 21 not shown) of the data storage device. (Fig. 4, 12a; ¶33)
Regarding claim 20, Matsumoto discloses the data storage device of claim 16, wherein the controller means (Fig. 4, 11; ¶34) is mounted directly to the surface of the PCB (Fig. 4, 21; ¶30) using a reflow soldering process.
The presence of process limitations, "reflow soldering process" on product
claims, which product does not otherwise patentably distinguish over prior art, cannot
impart patentability to the product
Allowable Subject Matter
Claims 1-7,9-10,12-14, 21-23 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art US-20190148349-A1 discloses a controller and a memory device bonded to a PCB, a wire coupled to an interposer that electrically connects the memory device to the controller through a trace. The wire is not coupled to the trace. US-20230268327-A1 discloses a substrate comprising a memory device and a controller electrically connected to each other through a conductive trace. However the memory chip is not direct bonded to the substrate.( US-7547961-B2, US-9947644-B2,US-20230260889-A1, US-20230137512-A1 , US-20200066701-A1 )discloses a memory device direct bonded to a substrate and electrically connected to a substrate trace by wire bond and a controller bonded to the substrate by solder. It is silent on the wire connected the controller to the memory through a trace. KR-102247916-B1 discloses the first controller 500 may be provided on the center of the package substrate 300 and electrically connected to the package substrate 300 through solder balls 504. The first chip stack 100 may be electrically connected to the first controller 500 through first bonding wires 415 connecting the first electrical pads 105 and the package substrate 300.KR-102247916-B1 is silent on connecting the wire to a trace that is electrically connected to the controller.
Regarding claim 1, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: "a bond wire having …a second end coupled to a signal trace…and the bond wire electrically couples the memory device to the controller via the signal trace”, as recited in Claim 1, with the remaining features.
Regarding claim 10, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " having …a second end coupled to the signal trace, the signal trace establishing a communication path between the memory device and the controller;”, as recited in Claim 10, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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