DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noh (US Publication 20230420039).
Regarding claim 1, Noh teaches a semiconductor chip, comprising:
a first intellectual property (IP) block (Fig. 7A, 100);
a second IP block (Fig. 7A, block8) and a third IP block around the first IP block (Fig. 7A, block 1);
a multiple metal layer stack over the first IP block, the second IP block and the third IP block (Fig. 7A, all the connections, including word lines and bit lines [see paragraph 3], that couple all of the memory cells and controllers would be in multiple layers [at least multiple connections/layers in a one single three dimensional direction] and would be stacked over the cells and controller in the one direction – see figure 10, if they are not ‘over’ they would be under which could be read on simply by flipping the substrate/IC/memory chip 300); and
an interconnect structure, situated in an upper portion of the multiple metal layer stack (Fig. 7A, simply connections shown in figure 7A between 100 and 201-204), configured for connecting the first IP block and the second IP block, wherein at least a part of the interconnect structure extends across and over the third IP block (Fig, 7A, interconnects between 100 and logic controllers).
Regarding claim 15, Noh teaches the limitations of claim 1 upon which claim 15 depends.
Noh teaches further comprising a plurality of super buffers disposed on a midway of the interconnection between the first IP block and the second IP block (Fig. 7A, logic circuits between 100 and block8).
Regarding claim 16, Noh teaches the limitations of claim 15 upon which claim 16 depends.
Noh teaches wherein the plurality of super buffers comprise a first super buffer, a second super buffer and a third super buffer (Fig. 7A, logic circuits from left to right), wherein the first super buffer includes a transmitting cell, the second super buffer includes an intermediate cell, and the third super buffer includes a receiving cell (Fig. 3, logic circuit with cells 211, 214, and 212).
Regarding claim 17, Noh teaches the limitations of claim 16 upon which claim 17 depends.
Noh teaches wherein the third super buffer is smaller than the first super buffer and further smaller than the second super buffer (para 25, different memory type and different buffer size, para 144).
Regarding claim 18, Noh teaches the limitations of claim 16 upon which claim 18 depends.
Noh teaches wherein the plurality of super buffers further comprises: a fourth super buffer (Fig. 7A, logic circuit) that includes another intermediate cell (Fig. 3, logic circuit with cells 211, 214, and 212), wherein the fourth super buffer is situated at a midway between the second super buffer and the third super buffer (Fig. 7A, logic circuit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US Publication 20230420039) in view of Or-Bach et al (US Publication 20170207214).
Regarding claim 2, Noh teaches the limitations of claim 1 upon which claim 2 depends.
Noh does not specifically teach wherein the upper portion of the multiple metal layer stack has a lower resistance than a lower portion of the multiple metal layer stack.
Or-Bach teaches wherein the upper portion of the multiple metal layer stack has a lower resistance than a lower portion of the multiple metal layer stack (para 98, "wider (more conductive)").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Noh to include the multiple metal layer stack with a lower resistance than a lower portion of the metal stack as taught by Or-Bach in order to improve the conductivity of the interconnections to improve the reliability and operability of the device.
Regarding claim 3, Noh as modified teaches the limitations of claim 2 upon which claim 3 depends.
Noh teaches further comprising a super buffer disposed on a midway of the interconnection between the first IP block and the second IP block (Fig. 7A, logic circuit between 100 and block8).
Regarding claim 4, Noh as modified teaches the limitations of claim 3 upon which claim 4 depends.
Noh teaches wherein the super buffer comprises a transmitting cell, an intermediate cell and a receiving cell (Fig. 3, 211, 214, and 212).
Regarding claims 5 and 9-11, Noh as modified teaches the limitations of claim Y upon which claim x depends.
Noh does not specifically teach:
[claim 5] wherein an input pin and an output pin of each of the transmitting cell, the intermediate cell and the receiving cell are situated in a middle portion of the multiple metal layer stack, wherein the middle portion is under the upper portion.
[claim 9] wherein the input pin and the output pin of the intermediate cell are situated at the same metal layer of the middle portion of the multiple metal layer stack.
[claim 10] wherein the input pin and the output pin of the transmitting cell are respectively situated at a first conductive layer and a second conductive layer of the middle portion of the multiple metal layer stack, and the second conductive layer is above the first conductive layer and separated from the first conductive layer by other conductive layers.
[claim 11] wherein the input pin and the output pin of the receiving cell are respectively situated at the second conductive layer and the first conductive layer.
Or-Bach teaches
[claim 5] wherein an input pin and an output pin of each of the transmitting cell, the intermediate cell and the receiving cell are situated in a middle portion of the multiple metal layer stack, wherein the middle portion is under the upper portion (para 107, "layer of stratum", Fig. 9, 908).
[claim 9] wherein the input pin and the output pin of the intermediate cell are situated at the same metal layer of the middle portion of the multiple metal layer stack (para 107, "layer of stratum", Fig. 9, 908).
[claim 10] wherein the input pin and the output pin of the transmitting cell are respectively situated at a first conductive layer and a second conductive layer of the middle portion of the multiple metal layer stack, and the second conductive layer is above the first conductive layer and separated from the first conductive layer by other conductive layers (para 107, "layer of stratum", Fig. 9, 908).
[claim 11] wherein the input pin and the output pin of the receiving cell are respectively situated at the second conductive layer and the first conductive layer (para 107, "layer of stratum", Fig. 9, 908).
Interconnection with multilayer metallization of logic circuits, buffers, addressing circuits and other associated circuits within memory ICs is well known within the art therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Noh to include the multiple metal layer stack and associated connectivity as taught by Or-Bach in order to improve the conductivity of the interconnections to improve the reliability and operability of the device.
Regarding claim 6, Noh as modified teaches the limitations of claim 5 upon which claim 6 depends.
Noh teaches wherein a metal layer is over the transmitting cell, the intermediate cell and the receiving cell, and is configured for connecting the interconnect structure and the input pins and the output pins of the receiving cell, the intermediate cell and the transmitting cell (Fig. 7A, interconnect between logic circuits and 100).
Regarding claim 7, Noh as modified teaches the limitations of claim 6 upon which claim 7 depends.
Noh teaches wherein the metal layer is configured for connecting power/ground signal lines that are situated in the middle portion of the multiple metal layer stack and arranged in parallel (Fig. 7A, interconnect between 100 and 201-204).
Regarding claim 8, Noh as modified teaches the limitations of claim 7 upon which claim 8 depends.
Noh teaches wherein the metal layer extends continuously over the power/ground signal lines (Fig. 7A, interconnect between 100 and 201-204).
Noh does not specifically teach a width of the metal layer is greater than a width of each of the power/ground signal lines.
Or-Bach teaches a width of the metal layer is greater than a width of each of the power/ground signal lines (para 98, "wider (more conductive)").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Noh to include the metal layer conductor width variance as taught by Or-Bach in order to improve the conductivity of the interconnections to improve the reliability and operability of the device.
Regarding claim 12, Noh as modified teaches the limitations of claim 3 upon which claim 12 depends.
Noh teaches further comprising a register between the super buffer and the second IP block, wherein the register is configured for connecting a receiving cell of the super buffer and the second IP block (Fig. 3, 213 between 210 and block8).
Regarding claim 13, Noh as modified teaches the limitations of claim 3 upon which claim 13 depends.
Noh teaches wherein an edge of the super buffer is aligned with a power/ground signal line that is situated beneath the upper portion of the multiple metal layer stack (Fig. 7A, edge of logic circuit aligned with metal layer/interconnect between 100 and 201-204)
Regarding claim 14, Noh as modified teaches the limitations of claim 3 upon which claim 14 depends.
Noh teaches wherein the super buffer is disposed near an edge of the third IP block (Fig. 10, logic circuit near block1 edge).
Regarding claim 19, Noh teaches the limitations of claim 1 upon which claim 19 depends.
Noh does not specifically teach wherein the interconnect structure comprises a plurality of metal wires arranged in parallel, and a width of each of the plurality of the metal wires of the interconnect structure is greater than twice a width of a metal wire in a middle portion of the multiple metal layer stack.
Or-Bach teaches wherein the interconnect structure comprises a plurality of metal wires arranged in parallel, and a width of each of the plurality of the metal wires of the interconnect structure is greater than twice a width of a metal wire in a middle portion of the multiple metal layer stack (para 98, "wider (more conductive)").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Noh to include the metal layer conductor width variance as taught by Or-Bach in order to improve the conductivity of the interconnections to improve the reliability and operability of the device.
Regarding claim 20, Noh teaches the limitations of claim 1 upon which claim 20 depends.
Noh does not specifically teach further comprising: a power/ground routing structure, situated in the upper portion of the multiple metal layer stack and separated from the interconnect structure, wherein the power/ground routing structure supplies power to the first IP block, the second IP block and the third IP block.
Or-Bach teaches further comprising: a power/ground routing structure, situated in the upper portion of the multiple metal layer stack and separated from the interconnect structure, wherein the power/ground routing structure supplies power to the first IP block, the second IP block and the third IP block (para 107, Fig. 9, 910).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Noh to include the power/ground routing structure as taught by Or-Bach in order to improve the operability of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gu et al (US Publication 20250036514) – Memory error prediction method and apparatus, and device.
Pilolli et al (US Publication 20240046976) – Write duty cycle calibration on a memory device.
Kim et al (US Publication 20210384186) – Integrated circuit including simple cell interconnection and method of designing the same.
Lim et al (US Publication 20200312379) – Semiconductor memory device including parallel structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818