DETAILED ACTION
This office action is in response to the application filed on June 8, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicants’ arguments and amendments filed on June 8, 2026, in response to the office action mailed on March 27, 2026, have been fully considered. Accordingly, claims 1-20 are currently pending in this application.
Information Disclosure Statement
The information disclosure statements submitted on 7/28/2023, 2/7/2024, 12/23/2025 and 6/8/2026 are being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitations are: a first substrate means for providing electrical communication to one or more electrical components coupled to the first substrate means; one or more receiving means electrically connected to the first substrate means and for providing electrical communication between the first substrate means and one or more other substrate means; one or more first storage means each for storing an amount of electrical charge, each of the one or more first storage means being electrically connected to the first substrate means by a respective electrical connection means; a second substrate means for providing electrical communication to one or more electrical components coupled to the second substrate means, the second substrate means being electrically connected to the one or more receiving means and oriented generally perpendicular to the first substrate means; one or more second storage means each for storing an amount of electrical charge, each of the one or more second storage means being electrically connected to the second substrate means by a respective electrical connection means; a housing means for substantially enclosing each of the first substrate means, the second substrate means, the one or more receiving means, the one or more first storage means, and the one or more second storage means, the housing means comprising: a bottom surface and a top surface, the first substrate means being positioned between the bottom surface and top surface of the housing in claim 18.
Additionally, such claim limitations are: a third substrate means for providing electrical communication to one or more electrical components coupled to the third substrate means, the third substrate means being electrically connected to the one or more receiving means and oriented generally perpendicular to the first substrate means and spaced from the second substrate means; and one or more third storage means each for storing an amount of electrical charge, each of the one or more third storage means being electrically connected to the third substrate means by a respective electrical connection means in claim 19.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Periaman (US 2008/0315388) in view of Hung (US 2021/0120672).
With respect to Claim 1, Periaman shows (Fig. 1) most aspects of the current invention including a semiconductor device package comprising:
a first substrate (108) having a top planar surface and a bottom planar surface;
one or more receiving ports (118) electrically connected to the first substrate;
one or more first semiconductor dies (104) electrically connected to and mounted directly on the first substrate
a second substrate (110) having a top planar surface and a bottom planar surface, the second substrate being mechanically mounted on and electrically connected to the first substrate (108) by a corresponding receiving port of the one or more receiving ports (118), the second substrate being detachable coupled to the first substrate via the corresponding receiving port of the one or more receiving ports (118), and the top planar surface of the second substrate being oriented generally perpendicular to the top planar surface of the first substrate
one or more second semiconductor dies (112/114) electrically connected to and mounted directly on the second substrate
However, Periaman does not show a housing substantially enclosing each of the first substrate, the second substrate, the one or more receiving ports, the one or more first semiconductor dies, and the one or more second semiconductor dies, the housing comprising: a bottom surface and a top surface, the first substrate being positioned between the bottom surface and top surface of the housing, a first hollow protrusion extending upwardly from the top surface of the housing proximate one of the one or more receiving ports, the second substrate and the one or more second semiconductor dies being at least partially positioned within the first hollow protrusion.
On the other hand, and in the same field of endeavor, Hung teaches (Fig. 8,9B) a first substrate (92) having a top planar surface and a bottom planar surface, one or more first semiconductor dies electrically connected to and mounted directly on the first substrate (par 34), a second substrate (93) having a top planar surface and a bottom planar surface, the top planar surface of the second substrate being oriented generally perpendicular to the top planar surface of the first substrate, one or more second semiconductor dies electrically connected to and mounted directly on the second substrate and a housing (91) substantially enclosing each of the first substrate, the second substrate, the one or more first semiconductor dies, and the one or more second semiconductor dies, the housing comprising: a bottom surface and a top surface, the first substrate being positioned between the bottom surface and top surface of the housing. Furthermore, Hung teaches a first hollow protrusion (91c) extends upwardly from the top surface of the housing proximate to an area of the first substrate which the second substrate is electrically connected to the first substrate, and further the second substrate and the one or more second semiconductor dies being at least partially positioned within the first hollow protrusion. Hung teaches doing so in some embodiments to provide more media packages than can fit on a single main board. Also, Hung teaches that the enclosure is used to surround the device and provide protection to electrical components in the device and further may function as a metal heatsink to dissipate heat from the electrical components in the device.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to implement the housing as claimed by the applicant, in the device of Periaman, because enclosures/housings are well-known in the semiconductor packing art to provide more media packages than can fit on a single main board and lastly, and the enclosure/housing is used to surround the device and provide protection to electrical components in the device and further may function as a metal heatsink to dissipate heat from the electrical components in the device, as taught by Hung, and implementing the enclosure/housing for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 3, Hung shows (Fig. 8,9B) wherein the one or more first semiconductor dies include a first set of NAND dies and the one or more second semiconductor dies include a second set of NAND dies.
With respect to Claim 4, Hung shows (Fig. 8,9B) wherein the second set of NAND dies includes at least twice as many NAND dies as the first set of NAND dies.
With respect to Claim 5, Hung shows (Fig. 8,9B) wherein the one or more receiving ports (94) includes a first receiving port and a second receiving port each electrically connected to the first substrate and spaced from one another.
With respect to Claim 6, Periaman shows (Fig. 1) a second substrate (110) having a top planar surface and a bottom planar surface, the second substrate being mechanically mounted on and electrically connected to the first substrate (108) by a corresponding receiving port of the one or more receiving ports (118), the second substrate being detachable coupled to the first substrate via the corresponding receiving port of the one or more receiving ports (118), and the top planar surface of the second substrate being oriented generally perpendicular to the top planar surface of the first substrate and one or more second semiconductor dies (112/114) electrically connected to and mounted directly on the second substrate. Furthermore, Hung shows an arrangement in which a third substrate (95), may be formed in a similar method to the second substrate.
The courts have held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced: therefore, a third substrate, wherein the second substrate is electrically connected to the first receiving port and the third substrate electrically is mechanically mounted on and electrically connected to the first substrate via the second receiving port; and one or more third semiconductor dies electrically connected to and mounted directly on the third substrate, wherein the third substrate is detachably coupled to the first substrate via the second receiving port claimed by the applicant is therefore only considered to be a duplication of the package arrangement disclosed by Periaman in view of Hung that a person having ordinary skill in the routing art would have been able to implement in the design of the package structure using routine layout techniques based, among other things, on package sizes, number of semiconductor dies, size of the housing, etc. (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) )), since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the perpendicular arrangement is provided for the second substrate and one or more second semiconductor dies, as already suggested by Periaman.
With respect to Claim 7, Hung shows (Fig. 8,9B) wherein the one or more first semiconductor dies include a first set of NAND dies, the one or more second semiconductor dies include a second set of NAND dies, and the one or more third semiconductor dies include a third set of NAND dies.
With respect to Claim 8, Hung shows (Fig. 8,9B) wherein each of the second set of NAND dies and third set of NAND dies includes at least twice as many NAND dies as the first set of NAND dies.
With respect to Claim 9, Hung shows (Fig. 8,9B) wherein the housing substantially encloses each of the first, second, and third substrates and each of the one or more first, second, and third semiconductor dies, wherein the first hollow protrusion (91c) is proximate the first receiving port, and wherein the housing further comprises: a second hollow protrusion (91d) extending upwardly from the top surface of the housing proximate the second receiving port, the third substrate and the one or more third semiconductor dies being at least partially positioned within the second hollow protrusion.
With respect to Claim 17, Periaman shows (Fig. 1) wherein the one or more receiving ports are each through hole mounts electrically connected to the first substrate.
With respect to Claim 18, Periaman shows (Fig. 1) most aspects of the current invention including a semiconductor device package comprising:
a first substrate means (108) for providing electrical communication to one or more electrical components coupled to the first substrate means
one or more receiving means (118) electrically connected to the first substrate means and for providing electrical communication between the first substrate means and one or more other substrate means
one or more first storage means (104) each for storing an amount of electrical charge, the one or more first storage means being electrically connected to the first substrate means by a respective electrical connection means
a second substrate means (110) for providing electrical communication to one or more electrical components coupled to the second substrate means, the second substrate means being mechanically mounted on and electrically connected to the first substrate means by the one or more receiving means (118) and oriented generally perpendicular to the first substrate means, the second substrate means being detachably coupled to the first substrate means by the one or more receiving means
one or more second storage means (112/114) each for storing an amount of electrical charge, each of the one or more second storage means being electrically connected to the second substrate means by a respective electrical connection means
However, Periaman does not show a housing substantially enclosing each of the first substrate means, the second substrate means, the one or more receiving means, the one or more first storage means, and the one or more second storage means, the housing means comprising: a bottom surface and a top surface, the first substrate means being positioned between the bottom surface and top surface of the housing, a first hollow protrusion extending upwardly from the top surface of the housing means proximate one of the one or more receiving means, the second substrate means and the one or more second storage means being at least partially positioned within the first hollow protrusion.
On the other hand, and in the same field of endeavor, Hung teaches (Fig. 8,9B) a first substrate (92) having a top planar surface and a bottom planar surface, one or more first semiconductor dies electrically connected to and mounted directly on the first substrate (par 34), a second substrate (93) having a top planar surface and a bottom planar surface, the top planar surface of the second substrate being oriented generally perpendicular to the top planar surface of the first substrate, one or more second semiconductor dies electrically connected to and mounted directly on the second substrate and a housing (91) substantially enclosing each of the first substrate, the second substrate, the one or more first semiconductor dies, and the one or more second semiconductor dies, the housing comprising: a bottom surface and a top surface, the first substrate being positioned between the bottom surface and top surface of the housing. Furthermore, Hung teaches a first hollow protrusion (91c) extends upwardly from the top surface of the housing proximate to an area of the first substrate which the second substrate is electrically connected to the first substrate, and further the second substrate and the one or more second semiconductor dies being at least partially positioned within the first hollow protrusion. Hung teaches doing so in some embodiments to provide more media packages than can fit on a single main board. Also, Hung teaches that the enclosure is used to surround the device and provide protection to electrical components in the device and further may function as a metal heatsink to dissipate heat from the electrical components in the device.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to implement the housing as claimed by the applicant, in the device of Periaman, because enclosures/housings are well-known in the semiconductor packing art to provide more media packages than can fit on a single main board and lastly, and the enclosure/housing is used to surround the device and provide protection to electrical components in the device and further may function as a metal heatsink to dissipate heat from the electrical components in the device, as taught by Hung, and implementing the enclosure/housing for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 19, Periaman shows (Fig. 1) a second substrate means (110) having a top planar surface and a bottom planar surface, the second substrate being mechanically mounted on and electrically connected to the first substrate means (108) by a corresponding receiving means (118), the second substrate means being detachable coupled to the first substrate means via the corresponding receiving means (118), and the top planar surface of the second substrate being oriented generally perpendicular to the top planar surface of the first substrate and one or more second semiconductor dies (112/114) electrically connected to and mounted directly on the second substrate. Furthermore, Hung shows an arrangement in which a third substrate means (95), may be formed in a similar method as the second substrate.
The courts have held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced: therefore, a third substrate means, for providing electrical communication to one or more electrical components coupled to the third substrate means, the third substrate means being mechanically mounted on and electrically connected to the first substrate by the one or more receiving means and oriented generally perpendicular to the first substrate means and spaced from the second substrate means, the third substrate means being detachably coupled to the first substrate means via the one or more receiving means, one or more third storage means each for storing an amount of electrical charge, each of one or more third storage means being electrically connected to the second substrate means by a respective electrical connection means claimed by the applicant is therefore only considered to be a duplication of the package arrangement disclosed by Periaman in view of Hung that a person having ordinary skill in the routing art would have been able to implement in the design of the package structure using routine layout techniques based, among other things, on package sizes, number of semiconductor dies, size of the housing, etc. (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) )), since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the perpendicular arrangement is provided for the second substrate and one or more second semiconductor dies, as already suggested by Periaman.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Periaman in view of Hung and in further view of Nakamichi (US 2021/0208428).
With respect to Claim 2, Periaman in view of Hung shows most aspects of the current invention. However, the combination of references do not show wherein the housing has a width of about 33.75 mm, a length of about 118.75 mm and a height of about 25.00 mm.
On the other hand, and in the same field of endeavor, Nakamichi teaches (Fig. 8) a semiconductor device package comprising a housing (2) substantially enclosing functional elements and semiconductor devices, wherein the housing has dimensions including a width of about 5-20 mm, a length of about 30-100 mm and a height of about 5-20 mm.
Regarding claim 2, the courts have held that differences in the dimensions of the housing will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimensions of the housing are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the dimensions of the housing and similar dimensions of the housing are known in the art (see e.g. Nakamichi), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Periaman in view of Hung.
Criticality: The specification contains no disclosure of either the critical nature of the claimed dimensions of the housing or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Periaman in view of Hung and in further view of Bollesen (US 5,963,427).
With respect to Claim 10, Periaman in view of Hung shows most aspects of the current invention. However, the combination of references do not show further comprising a heat sink mounted on the top surface of the housing and including a plurality of fins, each of the plurality of fins being positioned between the first and second hollow protrusions of the housing.
On the other hand, and in the same field of endeavor, Bollesen teaches (Fig. 2) a semiconductor device package comprising a housing (40) substantially enclosing a first substrate, a second substrate, one or more first semiconductor dies, and one or more second semiconductor dies, the housing comprising a bottom surface and a top surface, a first hollow protrusion (inside protrusion 42 on left side) extending upwardly from the top surface of the housing, and further comprises a second hollow protrusion (inside protrusion 42 on right side) extending upwardly from the top surface and further comprising a heat sink (40; integrated with the housing) mounted on the top surface of the housing and including a plurality of fins (44), each of the plurality of fins being positioned between the first and second hollow protrusions of the housing. Bollesen teaches internal horizontal fins are provided for the heat sink, with a gap in the middle, in order to allow manufacture by extrusion.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have further comprising a heat sink mounted on the top surface of the housing and including a plurality of fins, each of the plurality of fins being positioned between the first and second hollow protrusions of the housing in the device of Periaman in view of Hung, as taught by Bollesen which provides internal horizontal fins for the heat sink, with a gap in the middle, in order to allow manufacture by extrusion.
With respect to Claim 11, Bollesen teaches (Fig. 2) wherein the heat sink is integrally formed with the housing.
With respect to Claim 12, Bollesen teaches (Fig. 2) further comprising: one or more thermally conductive layers (thermal conductive balls), each thermally conductive layer of the one or more thermally conductive layers mounted directly onto a surface of a corresponding semiconductor die of the one or more first, second, and third semiconductor dies, wherein each thermally conductive layer extends between the surface of the corresponding semiconductor die to an adjacent interior surface of the housing.
With respect to Claim 13, Bollesen teaches (Fig. 1) wherein each fin of the plurality of fins extends upwardly from the top surface of the housing and are generally perpendicular to the top surface of the housing
With respect to Claim 14, Bollesen teaches (Fig. 2) wherein the first and second hollow protrusions each have a width that is greater than a width of an individual fin of the plurality of fins.
Allowable Subject Matter
Claims 15-16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 20, the prior art of record fails to disclose or suggest a housing comprising a first hollow protrusion extending upwardly from the top surface of the housing directly above the first receiving port, the second substrate being at least partially positioned within the first hollow protrusion; and a second hollow protrusion extending upwardly from the top surface of the housing proximate directly above the second receiving port, the third substrate being at least partially positioned within the second hollow protrusion; and a heat sink mounted on the top surface of the housing exterior to the internal cavity and including a plurality of fins, each of the plurality of fins being positioned between the first and second hollow protrusions of the housing.
Examiner's comments: the closest prior art references (Periaman US 2008/0315388; Hung US 2021/0120672; Chang US 2022/0310570; Baek US 8,456,000; Bezama US 2010/0117209) are all directed in part to a semiconductor device package comprising a first substrate having a top planar surface and a bottom planar surface substantially parallel to the top planar surface, one or more first NAND dies electrically connected to and mounted directly on the first substrate, a second substrate having a top planar surface and a bottom planar surface mechanically mounted on and electrically connected to the first substrate via the first receiving port, such that the top planar surface of the second substrate is perpendicular to the top planar surface of the first substrate, and such that the second substrate is detachably coupled to the first substrate via the first receiving port, one or more second NAND dies electrically connected to and mounted directly on the second substrate, a third substrate having a top planar surface and a bottom planar surface mechanically mounted on and electrically connected to the first substrate via the second receiving port, such that the top planar surface of the third substrate is perpendicular to the top planar surface of the first substrate, and such that the third substrate is detachably coupled to the first substrate via the second receiving port, similar to the instant invention.
However, the following references do neither anticipates nor renders obvious the following features of a housing comprising a first hollow protrusion extending upwardly from the top surface of the housing directly above the first receiving port, the second substrate being at least partially positioned within the first hollow protrusion; and a second hollow protrusion extending upwardly from the top surface of the housing proximate directly above the second receiving port, the third substrate being at least partially positioned within the second hollow protrusion; and a heat sink mounted on the top surface of the housing exterior to the internal cavity and including a plurality of fins, each of the plurality of fins being positioned between the first and second hollow protrusions of the housing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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