DETAILED ACTION
This Office Action is in response to the election filed on 13 April 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-17 and 21-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 2023/0086084 A1; hereinafter Yun), in view of Cheng et al. (US 2020/0266060 A1; hereinafter Cheng).
In regards to claim 11, Yun teaches, e.g. in figs. 2, a method comprising:
forming lower semiconductor nanostructures ((NS-P) under (RL)) [0039], lower dummy nanostructures (SL-L) [0039], upper semiconductor nanostructures ((NS-P) over (RL)) [0039], and upper dummy nanostructures (SL-U) [0039];
replacing (fig. 2Q: partially) the lower dummy nanostructures with lower dielectric structures (evidenced by (IS-L)) [0057], the lower dielectric structures formed of a first dielectric material [0057];
replacing (fig. 2Q: partially) the upper dummy nanostructures with upper dielectric structures (evidenced by (IS-U)) [0053], the upper dielectric structures formed of the first dielectric material [0053].
Yun appears to teach, in a different embodiment, the limitations of the lower semiconductor nanostructures and the upper dummy nanostructures formed of a first semiconductor material, the upper semiconductor nanostructures and the lower dummy nanostructures formed of a second semiconductor material [0040]; and removing the first dielectric material at a faster rate than the first semiconductor material and the second semiconductor material ([0040]: different materials for different etch rate). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the multiple obvious variants and embodiments taught by Yun.
Yun appears to be silent as to, but does not preclude, the limitations of removing the lower dielectric structures and the upper dielectric structures with an etching process that selectively etches the first dielectric material. Chang teaches, e.g. in figs. 4-10, the limitations of removing the lower dielectric structures and the upper dielectric structures with an etching process that selectively etches the first dielectric material ((111-117) dummy nanostructures; (137A) replacement dielectric structures; fig. 9: replacing dielectric structures) ([0042]; [0059]; [0059]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Yun with the aforementioned limitations taught by Cheng to have a GAA device structure and a method for forming a GAA device that reduces parasitic capacitance (Cheng [0004]).
In regards to claim 12, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. Yun further teaches, e.g. in figs. 2, the limitations wherein removing the lower dielectric structures forms lower openings between the lower semiconductor nanostructures, removing the upper dielectric structures forms upper openings between the upper semiconductor nanostructures, and the method further comprises:
forming a lower gate structure (G-L) [0079] in the lower openings between the lower semiconductor nanostructures (fig. 2AK); and
forming an upper gate structure (G-U) [0079] in the upper openings between the upper semiconductor nanostructures (fig. 2AK).
In regards to claim 13, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. Yun further teaches, e.g. in figs. 2, the limitations wherein the first semiconductor material is silicon-germanium and the second semiconductor material is silicon [0038].
In regards to claim 14, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. Yun further teaches, e.g. in figs. 2, the limitations wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium [0038].
In regards to claim 15, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. The combination of Yun and Cheng appears to be silent as to the arrangement of steps recited in the limitations wherein the lower dummy nanostructures are replaced before the upper dummy nanostructures are replaced; however, Yun teaches multiple arrangements of steps (figs. 2M-2Q). It would have been obvious to one having ordinary skill in the art at the time the invention was made to rearrange the steps taught by the combination of Yun and Cheng such that the lower dummy nanostructures are replaced before the upper dummy nanostructures are replaced, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (1950).
In regards to claim 16, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. Yun further teaches the limitations wherein the lower dummy nanostructures are replaced after the upper dummy nanostructures are replaced (figs. 2M-2Q).
In regards to claim 17, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 11. Cheng further teaches, e.g. in figs. 6-9, the limitations further comprising: forming inner spacers (138) [0036] adjacent the lower dielectric structures (137) [0065] and the upper dielectric structures, the inner spacers formed of a second dielectric material ([0036], [0065]: (138) is a high-k material and (137) is a low-k material). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Yun with the aforementioned limitations taught by Cheng to have a GAA device structure and a method for forming a GAA device that reduces parasitic capacitance (Cheng [0004]).
In regards to claim 21, Yun teaches, e.g. in figs. 2, a method comprising:
forming an isolation structure (e.g. RL) [0039] between first semiconductor nanostructures ((NS-P) under (RL)) [0039] and second semiconductor nanostructures ((NS-P) over (RL)), the isolation structure further formed between (figs. 2) first dummy nanostructures (SL-L) [0039] and second dummy nanostructures (SL-U) [0039];
replacing (fig. 2Q: partially) the first dummy nanostructures with first dielectric structures (evidenced by (IS-L)) [0057], the first dielectric structures being formed of a dielectric material [0057];
replacing (fig. 2Q: partially) the second dummy nanostructures with second dielectric structures (evidenced by (IS-U)) [0057], the second dielectric structures being formed of the dielectric material [0057]; and
respectively, a first gate structure (G-L) [0079] and a second gate structure (G-U) [0079], the first gate structure wrapped around the first semiconductor nanostructures, the second gate structure wrapped around the second semiconductor nanostructures (fig. 2AK).
Yun appears to teach, in a different embodiment, the limitations of the first semiconductor nanostructures and the second dummy nanostructures formed of a first semiconductor material, the second semiconductor nanostructures and the first dummy nanostructures formed of a second semiconductor material [0040]; wherein replacing the first dummy nanostructures comprises removing the first dummy nanostructures with a first etching process that selectively etches the second semiconductor material at a faster rate than the first semiconductor material [0040]; and wherein replacing the second dummy nanostructures comprises removing the second dummy nanostructures with a second etching process that selectively etches the first semiconductor material at a faster rate than the second semiconductor material [0040]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the multiple obvious variants and embodiments taught by Yun.
Yun appears to be silent as to, but does not preclude, the limitations of removing the lower dielectric structures and the upper dielectric structures with an etching process that selectively etches the first dielectric material. Chang teaches, e.g. in figs. 4-10, the limitations of removing the lower dielectric structures and the upper dielectric structures with an etching process that selectively etches the first dielectric material ((111-117) dummy nanostructures; (137A) replacement dielectric structures; fig. 9: replacing dielectric structures) ([0042]; [0059]; [0059]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Yun with the aforementioned limitations taught by Cheng to have a GAA device structure and a method for forming a GAA device that reduces parasitic capacitance (Cheng [0004]).
In regards to claim 22, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Yun further teaches the limitations wherein replacing the first dummy nanostructures further comprises covering the second semiconductor nanostructures during the first etching process, and replacing the second dummy nanostructures further comprises covering the first semiconductor nanostructures during the second etching process (fig. 2M-2P: lower structures covered by (RL) when etching upper and upper structures covered by (211) when etching lower).
In regards to claim 23, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Yun further teaches, e.g. in figs. 2, the limitations wherein the first semiconductor material is silicon-germanium and the second semiconductor material is silicon [0038], the first semiconductor nanostructures being channel regions for p-type nanostructure field-effect transistors and the second semiconductor nanostructures being channel regions for n-type nanostructure field-effect transistors ([0027], [0033], [0066]).
In regards to claim 24, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Yun further teaches the limitations wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium [0038], the first semiconductor nanostructures being channel regions for n-type nanostructure field-effect transistors and the second semiconductor nanostructures being channel regions for p-type nanostructure field- effect transistors ([0027], [0033], [0066]).
In regards to claim 25, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Yun further teaches the limitations wherein replacing the first dielectric structures and the second dielectric structures comprises removing the first dielectric structures and the second dielectric structures with a third etching process that etches the dielectric material at a faster rate than the first semiconductor material and the second semiconductor material [0040].
In regards to claim 26, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Cheng further teaches, e.g. in figs. 6-9, the limitations further comprising:
recessing sidewalls of the first dielectric structures and the second dielectric structures to form sidewall recesses (137) [0065]; and
forming inner spacers in the sidewall recesses (138) [0036].
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Yun with the aforementioned limitations taught by Cheng to have a GAA device structure and a method for forming a GAA device that reduces parasitic capacitance (Cheng [0004]).
In regards to claim 27, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 21. Yun further teaches, e.g. in figs. 2, the limitations further comprising:
growing first source/drain regions adjacent the first semiconductor nanostructures, the first source/drain regions having a first conductivity type ([0027], [0033], [0066]); and
growing second source/drain regions adjacent the second semiconductor nanostructures, the second source/drain regions having a second conductivity type, the second conductivity type being opposite the first conductivity type ([0027], [0033], [0066]).
In regards to claim 28, Yun teaches, e.g. in figs. 2, a method comprising:
forming lower semiconductor nanostructures ((NS-P) under (RL)) [0039], lower dummy nanostructures (SL-L [0039]), upper semiconductor nanostructures ((NS-P) over (RL)) [0039], upper dummy nanostructures (SL-U) [0039], and an isolation structure (RL) [0039], the isolation structure formed between the lower semiconductor nanostructures and the upper semiconductor nanostructures (figs. 2), the isolation structure further formed between the lower dummy nanostructures and the upper dummy nanostructures (figs. 2);
replacing (fig. 2Q: partially) the lower dummy nanostructures with lower dielectric structures (evidenced by (IS-L)) [0057] formed of a first dielectric material [0057]; replacing (fig. 2Q: partially) the upper dummy nanostructures with upper dielectric structures (evidenced by (IS-U)) [0057] formed of the first dielectric material [0057];
forming a lower gate structure (G-L) [0079] wrapped around the lower semiconductor nanostructures and an upper gate structure (G-U) [0079] wrapped around the upper semiconductor nanostructures (fig. 2AK).
Yun appears to teach, in a different embodiment, the limitations of the lower semiconductor nanostructures and the upper dummy nanostructures formed of a first semiconductor material, the upper semiconductor nanostructures and the lower dummy nanostructures formed of a second semiconductor material [0040]; wherein replacing the lower dummy nanostructures comprises removing the lower dummy nanostructures with a first etching process that selectively etches the second semiconductor material at a faster rate than the first semiconductor material [0040]; wherein replacing the upper dummy nanostructures comprises removing the upper dummy nanostructures with a second etching process that selectively etches the first semiconductor material at a faster rate than the second semiconductor material [0040]; and removing dielectric structures with a third etching process that selectively etches the first dielectric material at a faster rate than the first semiconductor material and the second semiconductor material [0040]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to combine the multiple obvious variants and embodiments taught by Yun.
Yun appears to be silent as to, but does not preclude, the limitations of removing the lower dielectric structures and the upper dielectric structures. Chang teaches, e.g. in figs. 6-9, the limitations of removing the lower dielectric structures and the upper dielectric structures ((111-117) dummy nanostructures; (137A) replacement dielectric structures; fig. 9: replacing dielectric structures) ([0042]; [0059]; [0059]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Yun with the aforementioned limitations taught by Cheng to have a GAA device structure and a method for forming a GAA device that reduces parasitic capacitance (Cheng [0004]).
In regards to claim 29, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 28. Yun further teaches, e.g. in figs. 2, the limitations wherein replacing the lower dummy nanostructures further comprises covering the upper semiconductor nanostructures during the first etching process, and replacing the upper dummy nanostructures further comprises covering the lower semiconductor nanostructures during the second etching process (fig. 2M-2P: lower structures covered by (RL) when etching upper and upper structures covered by (211) when etching lower).
In regards to claim 30, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 28. Yun further teaches the limitations further comprising:
growing lower source/drain regions adjacent the lower semiconductor nanostructures, the lower source/drain regions having a first conductivity type ([0027], [0033], [0066]); and
growing upper source/drain regions adjacent the upper semiconductor nanostructures, the upper source/drain regions having a second conductivity type, the second conductivity type being opposite the first conductivity type ([0027], [0033], [0066]).
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yun and Cheng as applied to claim 17 above, and further in view of Lin et al. (US 2019/0165156 A1; hereinafter Lin).
In regards to claim 18, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 17. The combination of Yun and Cheng appears to be silent as to, but does not preclude, the limitations wherein the first dielectric material is silicon nitride, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with phosphoric acid. Lin teaches the limitations wherein the first dielectric material is silicon nitride, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with phosphoric acid [0045-0046]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Yun and Cheng with the aforementioned limitations taught by Lin to use an etchant with a desired specific selectivity (Lin [0045-0046]).
In regards to claim 19, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 17. The combination of Yun and Cheng appears to be silent as to, but does not preclude, the limitations wherein the first dielectric material is silicon oxide, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with dilute hydrofluoric acid. Lin teaches the limitations wherein the first dielectric material is silicon oxide, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with dilute hydrofluoric acid [0045-0046]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Yun and Cheng with the aforementioned limitations taught by Lin to use an etchant with a desired specific selectivity (Lin [0045-0046]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yun and Cheng as applied to claim 17 above, and further in view of Brar et al. (US 2007/0296028 A1; hereinafter Brar).
In regards to claim 20, the combination of Yun and Cheng teaches the limitations discussed above in addressing claim 17. The combination of Yun and Cheng appears to be silent as to, but does not preclude, the limitations wherein the first dielectric material is aluminum oxide, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with phosphoric acid and a sulfuric peroxide mixture. Brar teaches the limitations wherein the first dielectric material is aluminum oxide, the second dielectric material is silicon oxycarbonitride, and the etching process comprises a wet etch with phosphoric acid and a sulfuric peroxide mixture [0045]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Yun and Cheng with the aforementioned limitations taught by Brar to have a process with a specific etch selectivity (Brar [0045]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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