DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/16/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-14, 16 and 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "…a channel layer of the channel structure" in the second line of the claim. Claim 1 also recites the limitation "…a channel layer of the channel structure" in the sixth and seventh line of that claim. It is unclear whether the “a channel layer of the channel structure” of claim 11 is the same or different from the “a channel layer of the channel structure of claim 1. For purposes of examination, Examiner has interpreted “a channel layer of the channel structure” in claim 11 as “the channel layer of the channel structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11, 16, 21 and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (US 2023/0132530 A1, hereinafter Wu ‘530).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to Claim 1 Wu ‘530 discloses a memory device (Fig 1-5), comprising:
an alternating layer stack (120, Fig 4P, Para [0033]) comprising dielectric layers (121, Fig 4P, Para [0033]) and conductive layers (123, Fig 4P, Para [0033]) stacked in a first direction (Z direction as shown in Fig 4P);
a channel structure (130, Fig 4P, Para [0052]) extending through (130 extending through 120 disclosed in Fig 4P and Para [0052]) the alternating layer stack (120) in the first direction (Z direction) in a first region (101 (core region), Fig 1B and 4G, Para [0026]), wherein a first material layer (113, Fig 4P, Para [0074]) is disposed on (113 on 130 disclosed in Fig 4L) the channel structure (130), wherein the first material layer (113) comprises a conductive layer (113, Fig 4P, Para [0055] discloses 113 as polysilicon) in contact with a channel layer (136, Fig 4P, Para [0034 and 0073-0074]) of the channel structure (130); and
a first dummy channel structure (150, Fig 4P, Para [0042]) extending through (150 extending through 120 disclosed in Fig 4P and Para [0042]) the alternating layer stack (120) in the first direction (Z direction) in a second region (102 (staircase region), Fig 1B and 4G, Para [0026]) abutting the first region (101)(region 102 abutting 101 shown in Fig 1B), wherein a second material layer (165, Fig 4P, Para [0076]) is disposed on (165 on 150 disclosed in Fig 4P) the first dummy channel structure (150), wherein the first material layer (113) and the second material layer (165) are different materials (Para [0055] discloses 113 as polysilicon and Para [0045] discloses 165 as silicon oxide), wherein the first material layer (113) is spaced apart from (113 spaced apart from 150 in the X direction disclosed in Fig 4P; there are gaps between the vertical leg of 113 around 150 and vertical leg of 113 around 130) the first dummy channel structure (150) in a second direction (X direction as shown in Fig 4P), wherein the first direction (Z direction) is perpendicular (shown in axis of Fig 4P) to the second direction (X direction), wherein the first material layer (113) and the second material layer (165) are located on a first side (BACKSIDE, Fig 4P, Para [0074 and 0076]) of the alternating layer stack (120), wherein a peripheral circuit (Para [0029] discloses a periphery die (not shown) located on the front side of the semiconductor device 100) is located on a second side (FRONT/FACE, Fig 4P, Para [0029]) of the alternating layer stack (120), and wherein the first side (BACKSIDE) and the second side (FRONT/FACE) are opposite to each other (Fig 4P discloses BACKSIDE and FRONT/FACE opposite each other) along the first direction (Z direction).
With respect to Claim 2 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 further discloses wherein the second material layer (165) is disposed on the first material layer (113)(Fig 4P discloses layer 165 on layer 113).
With respect to Claim 3 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 further discloses wherein the second material layer (165) comprises a dielectric material (Para [0045] discloses 165 as silicon oxide).
With respect to Claim 4 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 further discloses wherein the first material layer (113) comprises a conductive material (Para [0055] discloses 113 as polysilicon).
With respect to Claim 5 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 discloses further comprising a second dummy channel structure (second 150 as shown in annotated Fig 1B of Wu ‘530) in the second region (102), wherein a third material layer (112, Fig 4P, Para [0074]) is disposed on the second dummy channel structure (second 150)(Fig 4P is a cross section of Fig 1B where a plurality of dummy structures 150 is disclosed, Para [0074] discloses 112 over backside of device).
With respect to Claim 6 Wu ‘530 discloses all limitations of the memory device of claim 5, and Wu ‘530 discloses further wherein the third material layer (112) comprises a conductive material (Para [0055] discloses 112 as polysilicon).
With respect to Claim 7 Wu ‘530 discloses all limitations of the memory device of claim 5, and Wu ‘530 discloses further wherein the second dummy channel structure (second 150) is filled with an insulating material (Para [0042] discloses 150 comprises one or more dielectric materials).
With respect to Claim 8 Wu ‘530 discloses all limitations of the memory device of claim 5, and Wu ‘530 does not expressly disclose wherein a depth of the first dummy channel structure is greater than a depth of the second dummy channel structure in the first direction.
However, the examiner notes that in Para [0058 and 0105] the applicants disclosure teaches wherein the depths and widths of dummy channels can vary during the manufacturing process and Para [0106-0107] disclose further steps may need to be taken to maintain the advantage of creating dielectric separation in the device. Having this mind, Wu ‘530 teaches dielectric dummy channels and methods to control the dielectric structures (Para [0027)]. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of creating dielectric separation in the device. See MPEP§2144.05 (II)(A),(B).
With respect to Claim 9 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 discloses further wherein the first dummy channel structure (150) is not electrically connected with the first material layer (113) (Para [0042] discloses 150 comprises one or more dielectric materials).
With respect to Claim 10. (Original) The memory device of claim 1, and Wu ‘530 does not expressly disclose wherein a depth of the first dummy channel structure is greater than a depth of the channel structure in the first direction.
However, the examiner notes that in Para [0058 and 0105] the applicants disclosure teaches wherein the depths and widths of dummy channels can vary during the manufacturing process and Para [0106-0107] disclose further steps may need to be taken to maintain the advantage of creating dielectric separation in the device. Having this mind, Wu ‘530 teaches dielectric dummy channels and methods to control the dielectric structures (Para [0027)]. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of creating dielectric separation in the device. See MPEP§2144.05 (II)(A),(B).
With respect to Claim 11 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 discloses further wherein the first material layer (113) is disposed on a channel layer (136) (Note Examiner interpretation of “a channel layer” as “the channel layer”) of the channel structure (130), and wherein the first material layer (113) is electrically connected with the channel layer (136)(Para [0037] discloses 136 electrically connected to 113).
With respect to Claim 16 Wu ‘530 discloses a memory system (Fig 1-5), comprising:
a controller (502, Fig 5, Para [0081]); and
a memory device (511, Fig 5, Para [0081]) coupled to the controller (502)(511 coupled to 502 disclosed in Fig 5 and Para [0081]), the memory device (511) comprising:
an alternating layer stack (120, Fig 4P, Para [0033]) comprising dielectric layers (121, Fig 4P, Para [0033]) and conductive layers (123, Fig 4P, Para [0033]) stacked in a first direction (Z direction as shown in Fig 4P);
a channel structure (130, Fig 4P, Para [0052]) extending through (130 extending through 120 disclosed in Fig 4P and Para [0052]) the alternating layer stack (120) in the first direction (Z direction) in a first region (101 (core region), Fig 1B and 4G, Para [0026]), wherein a first material layer (113, Fig 4P, Para [0074]) is disposed on (113 on 130 disclosed in Fig 4L) the channel structure (130), wherein the first material layer (113) comprises a conductive layer (113, Fig 4P, Para [0055] discloses 113 as polysilicon) in contact with a channel layer (136, Fig 4P, Para [0034 and 0073-0074]) of the channel structure (130); and
a first dummy channel structure (150, Fig 4P, Para [0042]) extending through (150 extending through 120 disclosed in Fig 4P and Para [0042]) the alternating layer stack (120) in the first direction (Z direction) in a second region (102 (staircase region), Fig 1B and 4G, Para [0026]) abutting the first region (101)(region 102 abutting 101 shown in Fig 1B), wherein a second material layer (165, Fig 4P, Para [0076]) is disposed on (165 on 150 disclosed in Fig 4P) the first dummy channel structure (150), wherein the first material layer (113) and the second material layer (165) are different materials (Para [0055] discloses 113 as polysilicon and Para [0045] discloses 165 as silicon oxide), wherein the first material layer (113) is spaced apart from (113 spaced apart from 150 in the X direction disclosed in Fig 4P; there are gaps between the vertical leg of 113 around 150 and vertical leg of 113 around 130) the first dummy channel structure (150) in a second direction (X direction as shown in Fig 4P), wherein the first direction (Z direction) is perpendicular (shown in axis of Fig 4P) to the second direction (X direction), wherein the first material layer (113) and the second material layer (165) are located on a first side (BACKSIDE, Fig 4P, Para [0074 and 0076]) of the alternating layer stack (120), wherein a peripheral circuit (Para [0029] discloses a periphery die (not shown) located on the front side of the semiconductor device 100) is located on a second side (FRONT/FACE, Fig 4P, Para [0029]) of the alternating layer stack (120), and wherein the first side (BACKSIDE) and the second side (FRONT/FACE) are opposite to each other (Fig 4P discloses BACKSIDE and FRONT/FACE opposite each other) along the first direction (Z direction).
With respect to Claim 21 Wu ‘530 discloses all limitations of the memory device of claim 1, and Wu ‘530 further discloses wherein the first material layer (113) is in contact with a sidewall and a bottom surface of the channel layer (136)(Fig 4P discloses 113 is in contact with a sidewall and bottom surface (surface facing BACKSIDE of device)).
With respect to Claim 23. (Previously Presented) The memory system of claim 16, wherein the first material layer (113) comprises a conductive source layer (Para [0037] discloses 113 in a common source layer) electrically connected (Para [0037] discloses 113 electrically connected to 136) to a channel layer (136) of the channel structure. (130)
Allowable Subject Matter
Claims 12-14, 22 and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claims 12-14, allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the features: “a staircase structure in a third region abutting the second region” along with the rest of the limitations of said claims.
Closest prior art of record Wu ‘530 teaches a staircase structure. However Wu ‘530 fails to disclose the staircase structure in the second region, Wu ‘530 discloses the staircase structure in the second region and Wu ‘530 can not be interpreted to include the staircase structure in a third region and still meet the claim limitations of claim 1.
Regarding Claim 13, allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the features: “wherein the contact structure is electrically connected with one of the conductive layers of the alternating stack” along with the rest of the limitations of said claims.
Closest prior art of record Wu ‘530 teaches a contact structure. However Wu ‘530 fails to disclose the contact structure in contact with one of the conductive layers of the stack, Wu ‘530 discloses the contact structure as a through contact that connects the memory device with a peripheral circuit and Wu ‘530 is not expressly open to suggest a contact structure connected to the conductive layers.
Regarding Claims 22 and 24, allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the features: “wherein an orthographic projection of the first dummy channel structure does not overlap with an orthographic projection of the first material layer” along with the rest of the limitations of said claims.
Closest prior art of record Wu ‘530 discloses a first dummy channel structure and a first material layer. However Wu ‘530 fails to disclose the first material layer is not over the first dummy structure and Wu ‘530 is not expressly open to suggest the first material layer not being over the dummy structure.
Regarding Claim 25, allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the features: “wherein the first material layer is in direct contact with the channel structure, and wherein the second material layer is in direct contact with the first dummy channel structure” along with the rest of the limitations of said claims.
Closest prior art of record Wu ‘530 discloses a first dummy channel structure and a channel structure and a first material layer and second material layer over the first dummy channel structure and channel structure. However Wu ‘530 fails to disclose the first material layer is in direct contact with the channel structure, and wherein the second material layer is in direct contact with the first dummy channel structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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