DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Examiner acknowledges amendments of claims 1 and 16, cancellation of claim 15 and the addition of new claims 21-25.
Drawings
Applicant’s cancellation of claim 15 makes moot the Drawing Objection made in the Office Action mailed on 02/20/2026 so therefore that drawing objection is withdrawn.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments of Claims 1 and 16, Applicant argues (Section III of Applicant Arguments) that prior art of record Han ‘536 “does not describe each and every element of Applicant's claims as examiner, or as amended, in as complete detail or arranged as in Applicant's claims”. Examiner respectfully disagrees as MPEP 2111.01(I)-(IV) and MPEP 2173.01 (I) instructs Examiner to use the broadest reasonable interpretation (BRI) of the claim language, reading the claim in its plain meaning; the ordinary and customary meaning given to the term by one of ordinary skill in the art. MPEP (MPEP 2145(VI)) states, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. Given this direction, prior art of record Han ‘536 does disclose each and every element of the recited limitations as they are written in Claim 1 and 16 in the Office Action mailed on 02/20/2026. Therefore Examiner finds Applicant’s Argument not persuasive and maintains the 35 USC § 102 rejection of Claim 1 and 16 made in the office action mailed on 02/20/2026.
Specific to the above argument, Applicant argues (Section III A of Applicant Arguments) that the Office Action of 02/20/2026 has incorrectly identified the recited claim element “first dummy channel structure”, that the proper element is not 620 of Han ‘536, rather it is the element 464 which is specifically labeled as a dummy memory channel structure. While we understand what Applicant is saying, element 620 meets the limitations of Claim 1 and 16 for a first dummy channel structure. There is nothing, except by name, that distinguishes 464 over 620 as the first dummy channel structure. Examiner again argues that limitations from the specification can not be read into the claims and holds the position that element 620 of Han ‘536 meets the element limitations of the first dummy channel structure as cited in claims 1 and 16. Therefore Examiner finds Applicant’s Argument not persuasive and maintains the 35 USC § 102 rejection of Claim 1 and 16 made in the office action mailed on 02/20/2026.
Applicant argues (Section III B of Applicant’s Arguments) that Han ‘536 does not meet the limitations of Claim 9 as the way the first material layer is formed in the instant application is different from the way that the first material layer (925) of Han ‘536 was formed, that, “The absence of the first material layer above the dummy channel structure is both the structural feature and the mechanism of isolation. Han discloses no equivalent process, structure or mechanism”. Applicant respectfully disagrees with this argument. Again, reading the claim in it’s BRI and not reading limitations from the specification into the claim, Examiner argues that the elements of Han ‘536 identified in the prior office action of 02/20/2026 meets the structural limitations of the claims. The mechanisms or methods used to create the elements of Claims 1 and 16, recited in the specification of the instant application, can not be read into the claim. Claim 1 and 16 are device claims and Han ‘536 meets the recited structural claim limitations of claim 1 and dependent claim 9 as shown in the Office action of 02/20/2026. Therefore Examiner finds Applicant’s Argument not persuasive and maintains the 35 USC § 102 rejection of Claim 1 and 16 made in the office action mailed on 02/20/2026.
Applicant argues (Section III C, D and E of Applicant’s Arguments) that Han ‘536 does not meet the limitations of newly added claims 21, 22 and 25 respectfully. Newly added claims 21-25 are addressed by Examiner in this Office Action below.
Claim Rejections - 35 USC § 112
Amendments made in Applicant Arguments/Remarks Made in an Amendment of 04/06/2026 overcome the previous 35 USC § 112 rejections of claims 1 and 16 made in the Office Action mailed on 02/20/2026, therefore 35 USC § 112 rejections of claims 1 and 16 in the Office Action mailed on 02/20/2026 are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (KR 20240047536 A, hereinafter Han ‘536).
With respect to Claim 1 Han ‘536 discloses a memory device (Fig 1-43), comprising:
an alternating layer stack (315/754, Fig 34, Para [0037 and 0040]) comprising dielectric layers (315, Fig 34, Para [0040]) and conductive layers (754, Fig 34, Para [0037]) stacked in a first direction (D1, Fig 2, Para [0012] discloses D1 as vertical, perpendicular from substrate);
a channel structure (462, Fig 4, Para [0046]) extending through the alternating layer stack (315/754) in the first direction (D1) in a first region (Region of cross section B-B’, Fig 2, Para [0014]), wherein a first material layer (925, Fig 4, Para [0058]) is disposed on the channel structure (462)(first material 925 on channel structure 462 shown in Fig 4); and
a first dummy channel structure (620, Fig 4, Para [0016]) extending through the alternating layer stack (315/754) in the first direction (D1) in a second region (Region of cross section C-C’, Fig 2, Para [0014]) abutting the first region (Region of cross section B-B’)(Fig 2 discloses second region abutting the first region), wherein a second material layer (950/960/970, Fig 4, Para [0077]) is disposed on the first dummy channel structure (620)(Fig 4 discloses 950/960/970 disposed on first dummy channel structure 620), wherein the first material layer (925) and the second material layer (950/960/970) are different materials (Para [0083] discloses 650 as silicon oxide and Para [0039] discloses 925 as doped polysilicon), wherein the first material layer (925) is spaced apart from the first dummy channel structure (620)(Fig 4 discloses no 925 around 620 therefore, 925 is spaced apart from 620) in a second direction (D2, Fig 2), and wherein the first direction (D1) is perpendicular (disclosed in axis of Fig 2) to the second direction (D2).
With respect to Claim 2 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein the second material layer (950/960/970) is disposed on the first material layer (925)(950/960/970 disposed on 925 disclosed in Fig 4).
With respect to Claim 3 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein the second material layer (950/960/970) comprises a dielectric material (Para [0083] discloses 650 as silicon oxide).
With respect to Claim 4 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein the first material layer (925) comprises a conductive material (Para [0039] discloses 925 as doped polysilicon).
With respect to Claim 5 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 discloses further comprising a second dummy channel structure (464, Fig 4, Para [0016]) in the second region (Region of cross section C-C’, Fig 2, Para [0014]), wherein a third material layer (454, Fig 4, Para [0062]) is disposed on the second dummy channel structure (464)(Fig 4 and Para [0062] disclose 454 on top of 464).
With respect to Claim 6 Han ‘536 discloses all limitations of the memory device of claim 5, and Han ‘536 discloses further wherein the third material layer (454) comprises a conductive material (Para [0071] discloses 454 as doped polysilicon).
With respect to Claim 7 Han ‘536 discloses all limitations of the memory device of claim 5, and Han ‘536 further discloses wherein the second dummy channel structure (464) is filled with an insulating material (Para [0071] discloses layer 444 (silicon oxide) fills structure 464).
With respect to Claim 8 Han ‘536 discloses all limitations of the memory device of claim 5, and Han ‘536 further discloses wherein a depth (depth of 620 in D1, vertical direction, as shown in Fig 4) of the first dummy channel structure (620) is greater than a depth (depth of 464 in D1, vertical direction, as shown in Fig 4) of the second dummy channel structure (464) in the first direction (D1)(depth of 620 greater than 464 disclosed in Fig 4).
With respect to Claim 9 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein the first dummy channel structure (620) is not electrically connected with the first material layer (925)(Fig 4 and Para [0056] discloses 620 isolated from 925 by 475).
With respect to Claim 10 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein a depth (depth of 620 in D1, vertical direction, as shown in Fig 4) of the first dummy channel structure (620) is greater than a depth (depth of 620 in D1, vertical direction, as shown in Fig 4) of the channel structure (462) in the first direction (D1)(depth of 620 greater than 462 disclosed in Fig 4).
With respect to Claim 11 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 further discloses wherein the first material layer (925) is disposed on a channel layer (416, Fig 4, Para [0067]) of the channel structure (462/466), and wherein the first material layer (925) is electrically connected with the channel layer (416)(Para [0067] discloses 416 in contact with 925, and Para [0071] discloses 416 as doped polysilicon, which would create an electrical connection with doped polysilicon of 925).
With respect to Claim 12 Han ‘536 discloses all limitations of the memory device of claim 1, and Han ‘536 discloses further comprising a staircase structure (staircase structure of 315/754 disclosed in Fig 3) in a third region (region II, Fig 2 and 3, Para [0020]) abutting (region II abutting region of C-C’ shown in Fig 2) the second region ((Region of cross section C-C’, Fig 2), wherein the staircase structure (staircase structure of 315/754 disclosed in Fig 3) comprises the alternating layer stack (315/754)(disclosed in Fig 3).
With respect to Claim 13 Han ‘536 discloses all limitations of the memory device of claim 12, and Han ‘536 discloses further comprising a contact structure (634, Fig 3, Para [0078]) in the third region (region II), wherein the contact structure (634) is electrically connected with one of the conductive layers (754) of the alternating layer stack (315/754)(Fig 3 and Para [0078] discloses 634 electrically connected to a layer of 754).
With respect to Claim 16 Han ‘536 disclose a memory system (Fig 1-43 and 50-53), comprising:
a controller (1220, Fig 50, Para [0228]); and
a memory device (1100, Fig 50, Para [0222]) coupled to the controller (disclosed in Fig 50 and Para [0229]), the memory device (1100) comprising:
an alternating layer stack (315/754, Fig 34, Para [0037 and 0040]) comprising dielectric layers (315, Fig 34, Para [0040]) and conductive layers (754, Fig 34, Para [0037]) stacked in a first direction (D1, Fig 2, Para [0012] discloses D1 as vertical, perpendicular from substrate);
a channel structure (462, Fig 4, Para [0046]) extending through the alternating layer stack (315/754) in a first direction (D1) (Note: Examiner interprets “a first direction” as “the first direction as described above) in a first region (Region of cross section B-B’, Fig 2, Para [0014]), wherein a first material layer (925, Fig 4, Para [0058]) is disposed on the channel structure (462)(first material 925 on channel structure 462 shown in Fig 4); and
a first dummy channel structure (620, Fig 4, Para [0016]) extending through the alternating layer stack (315/754) in the first direction (D1) in a second region (Region of cross section C-C’, Fig 2, Para [0014]) abutting the first region (Region of cross section B-B’)(Fig 2 discloses second region abutting the first region), wherein a second material layer (950/960/970, Fig 4, Para [0077]) is disposed on the first dummy channel structure (620)(Fig 4 discloses 950/960/970 disposed on first dummy channel structure 620), wherein the first material layer (925) and the second material layer (950/960/970) are different materials (Para [0083] discloses 650 as silicon oxide and Para [0039] discloses 925 as doped polysilicon), wherein the first material layer (925) is spaced apart from the first dummy channel structure (620)(Fig 4 discloses no 925 around 620 therefore, 925 is spaced apart from 620) in a second direction (D2, Fig 2), and wherein the first direction (D1) is perpendicular (disclosed in axis of Fig 2) to the second direction (D2).
Claims 1-2, 21-22 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2017/0358593 A1, hereinafter Yu ‘593).
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With respect to Claim 1 Yu ‘593 discloses a memory device (Fig. 1-15B), comprising:
an alternating layer stack (132/146, Fig 7A, Para [0117]) comprising dielectric layers (132, Fig 7A, Para [0058]) and conductive layers (146, Fig 7A, Para [0117]) stacked in a first direction (vertical direction as shown in annotated Fig 7A);
a channel structure (55, Fig 4A and 7A, Para [0087] discloses 55 comprising memory film layer, semiconductor layer, dielectric core and first and second semiconductor channels) extending through the alternating layer stack (132/146) in the first direction (vertical direction as shown in Fig 7A) in a first region (100, Fig 7A, Para [0052]), wherein a first material layer (10/6, Fig 7A, Para [0054]) is disposed on (10/6 disposed on structures 55 shown in Fig 7A) the channel structure (55); and
a first dummy channel structure (155, Fig 7A, Para [0087]) extending through (155 extending through 132/146 disclosed in Fig 7A) the alternating layer stack (132/146) in the first direction (vertical direction as shown in annotated Fig 7A) in a second region (500, Fig 7A, Para [0051]) abutting the first region (100)(500 abutting 100 disclosed in Fig 7A and Para [0052]), wherein a second material layer (760, Fig 7A, Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) is disposed on (Fig 7A discloses dielectric layer 760 (includes dielectric material under 500 as disclosed above) disposed on 155) the first dummy channel structure (155), wherein the first material layer (10/6) and the second material layer (760) are different materials (Para [0056 and 0055] discloses 10/6 as semiconductor material and Para [0054] discloses 155 as a dielectric such as silicate glass), wherein the first material layer (10/6) is spaced apart from (10/6 spaced apart from structures 155 disclosed in Fig 7A) the first dummy channel structure (155) in a second direction (horizontal direction as shown in annotated Fig 7A), and wherein the first direction (vertical direction as shown in annotated Fig 7A) is perpendicular to the second direction (horizontal direction as shown in annotated Fig 7A).
With respect to Claim 2. Yu ‘593 discloses all limitations of the memory device of claim 1, and Yu ‘593 further discloses wherein the second material layer (760) is disposed on (annotated Fig 7A and Para [0054] discloses 760 disposed over layer 10/6) the first material layer (10/6).
With respect to Claim 21 Yu ‘593 discloses all limitations of the memory device of claim 1, and Yu ‘593 further discloses wherein the first material layer (10/6) comprises a conductive source layer (Para [0055] discloses 10/6 as a source layer) electrically connected to a channel layer (Para [0092] discloses channel layer of 55 (specifically layer 601) electrically connected to 10/6) of the channel structure (55).
With respect to Claim 22 Yu ‘593 discloses all limitations of the memory device of claim 1, and Yu ‘593 further discloses wherein an orthographic projection (Fig 6A and 6B disclose 155 in opening in 10/6 in region 500 and Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) of the first dummy channel structure (155) does not overlap with an orthographic projection (Fig 6A and 6B disclose 10/6 not overlapping with dummy structure 155 as 10/6 is in region 100 and dummy channel structures 155 in region 500 and Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) of the first material layer (10/6).
With respect to Claim 25 Yu ‘593 discloses all limitations of the memory device of claim 2, and Yu ‘593 further discloses wherein the first material layer (10/6) is in direct contact with (10/6 in direct contact with 55 disclosed in Fig 7A and Para [0092]) the channel structure (55), and wherein the second material layer (760) is in direct contact with (155 in direct contact with 760 disclosed in Fig 7A) the first dummy channel structure (155).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Han ‘536 in view of Hyun (US 9,373,540 B2, hereinafter Hyun ‘540), in view of the following arguments.
With respect to Claim 14 Han ‘536 discloses all limitations of the memory device of claim 12,
but Han ‘536 fails to explicitly disclose further comprising a barrier structure in the third region, wherein the barrier structure comprises a conductive material.
Nevertheless, in a related endeavor (Fig 2A-2H of Hyun ‘540), Hyun ‘540 teaches further comprising a barrier structure (211/213, Fig 2H of Hyun ‘540, Col 6, Lines 48-52) in the third region (stair structure 207, Fig 2H of Hyun ‘540, Col 6, Lines 47), wherein the barrier structure (211/213) comprises a conductive material (Col 6, Line 50-52 disclose 211/213 as TiN and W).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hyun ‘540’s teaching of further comprising a barrier structure in the third region, wherein the barrier structure comprises a conductive material into Han ‘536’s device. Hyun ‘540 teaches a memory structure with a staircase region. Hyun ‘540 also teaches a memory structure and further teaches the use of a metal film barrier in the area where the contact meets the conductive layers of the stack. The ordinary artisan would have been motivated to modify Han ‘536 in the manner set forth above, at least, because, as Hyun ‘540 teaches in Col 7, Lines 16-21,the barrier films can form the pads to connect the contacts to the stair regions.
As incorporated, the barrier structure (211/213) of Hyun ‘540 would be used in the third region (II)(a staircase structure) of Han ‘536.
Claims 16 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘593 in view of Han ‘568, in view of the following arguments.
With respect to Claim 16 Yu ‘593 discloses a memory system (Fig. 1-15B), comprising:
a memory device (Para [0042] discloses device in Fig 1-15B is a memory device), the memory device comprising:
an alternating layer stack (132/146, Fig 7A, Para [0117]) comprising dielectric layers (132, Fig 7A, Para [0058]) and conductive layers (146, Fig 7A, Para [0117]) stacked in a first direction (vertical direction as shown in annotated Fig 7A);
a channel structure (55, Fig 4A and 7A, Para [0087] discloses 55 comprising memory film layer, semiconductor layer, dielectric core and first and second semiconductor channels) extending through the alternating layer stack (132/146) in the first direction (vertical direction as shown in Fig 7A) in a first region (100, Fig 7A, Para [0052]), wherein a first material layer (10/6, Fig 7A, Para [0054]) is disposed on (10/6 disposed on structures 55 shown in Fig 7A) the channel structure (55); and
a first dummy channel structure (155, Fig 7A, Para [0087]) extending through (155 extending through 132/146 disclosed in Fig 7A) the alternating layer stack (132/146) in the first direction (vertical direction as shown in annotated Fig 7A) in a second region (500, Fig 7A, Para [0051]) abutting the first region (100)(500 abutting 100 disclosed in Fig 7A and Para [0052]), wherein a second material layer (760, Fig 7A, Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) is disposed on (Fig 7A discloses dielectric layer 760 (includes dielectric material under 500 as disclosed above) disposed on 155) the first dummy channel structure (155), wherein the first material layer (10/6) and the second material layer (760) are different materials (Para [0056 and 0055] discloses 10/6 as a semiconductor material and Para [0054] discloses 155 as a dielectric such as silicate glass), wherein the first material layer (10/6) is spaced apart from (10/6 spaced apart from structures 155 disclosed in Fig 7A) the first dummy channel structure (155) in a second direction (horizontal direction as shown in annotated Fig 7A), and wherein the first direction (vertical direction as shown in annotated Fig 7A) is perpendicular to the second direction (horizontal direction as shown in annotated Fig 7A).
But Yu ‘593 fails to explicitly disclose a controller; and a memory device coupled to the controller.
Nevertheless, in a related endeavor (Fig 1-43 and 50-53 of Han ‘568), Han ‘568 teaches a controller (1220, Fig 50, Para [0228]); and a memory device (1100, Fig 50, Para [0222]) coupled to the controller (disclosed in Fig 50 and Para [0229]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Han ‘568’s teaching of a controller; and a memory device coupled to the controller into Yu ‘593’s device. Yu ‘593 discloses a memory device with channel structures and dummy channel structures and Yu ‘593 in Para [0049] discloses a memory system as Yu ‘593 discloses peripheral devices to support the memory device connected to the memory device. However, Yu ‘593 does not provide details of those devices. Han ‘568 teaches a memory device with channel structures and dummy channel structures and provides details for the peripheral control devices connected to the memory device. The ordinary artisan would have been motivated to modify Yu ‘593, in the manner set forth above, at least, because Han ‘568 provides details on connected devices to increase the functionality of the memory device.
As incorporated, the controller (1220) coupled to the memory device, as taught by Han ‘568 would be used such that controller 1220 of Han ‘568 would be coupled to the memory device of Yu’593.
With respect to Claim 23 Yu ‘593 as modified by Han ‘568 discloses all limitations of the memory system of claim 16, and Yu ‘593 further discloses wherein the first material layer (10/6) comprises a conductive source layer (Para [0055] discloses 10/6 as a source layer) electrically connected to a channel layer (Para [0092] discloses channel layer of 55 (specifically layer 601) electrically connected to 10/6) of the channel structure (55).
With respect to Claim 24 Yu ‘593 as modified by Han ‘568 discloses all limitations of the memory system of claim 16, wherein an orthographic projection (Fig 6A and 6B disclose 155 in opening in 10/6 in region 500 and Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) of the first dummy channel structure (155) does not overlap with an orthographic projection (Fig 6A and 6B disclose 10/6 not overlapping with dummy structure 155 as 10/6 is in region 100 and dummy channel structures 155 in region 500 and Para [0054] discloses the opening in 500 between layers 10/6 is filled with a dielectric material that is incorporated into layer 760) of the first material layer (10/6).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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