Prosecution Insights
Last updated: July 05, 2026
Application No. 18/361,219

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102§103
Filed
Jul 28, 2023
Priority
Oct 28, 2022 — RE 10-2022-0141510
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
48 currently pending
Career history
1687
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.6%
+16.6% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12 in the reply filed on 1/20/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 4, 5, 7, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20130075924). With respect to claim 1, Lin et al. teach a semiconductor package comprising (see figs. 1-17, particularly figs. 13a-14 and associated text): a first redistribution substrate (connecting structure right under 148); a semiconductor chip 124 disposed on the first redistribution substrate; a second redistribution substrate (connecting structure right over 148); an encapsulant 148 disposed between the first redistribution substrate and the second redistribution substrate and encapsulating the semiconductor chip; and a connection structure 250 disposed in the encapsulant, connecting an upper surface of the first redistribution substrate and a lower surface of the second redistribution substrate, and including a paste (meltable conductive material) bump 252. With respect to claim 2, Lin et al. teach the connection structure electrically connects the first redistribution substrate and the second redistribution substrate. See figs. 13a-14 and associated text. With respect to claim 3, Lin et al. teach the paste bump has a cross-sectional area that decreases in a plan view from an upper portion to a lower portion. See figs. 13a-14 and associated text. With respect to claim 4, Lin et al. teach the connection structure further includes a plating portion (metal connector right under 250) on at least one of an upper portion and a lower portion of the paste bump, and the paste bump includes a material different than that of the plating portion. See figs. 13a-14 and associated text. With respect to claim 5, Lin et al. teach the connection structure further includes a first bonding pad (connector right below 250) on the upper surface of the first redistribution substrate, and the paste bump is connected to the first bonding pad. See figs. 13a-14 and associated text. With respect to claim 7, Lin et al. teach the connection structure further includes a conductive pillar 252 extending from the lower surface of the second redistribution substrate, and the paste bump connects the conductive pillar and the first redistribution substrate. See figs. 13a-14 and associated text. With respect to claim 9, Lin et al. teach an upper package 124 (upper one) disposed on an upper surface of the second redistribution substrate; and a bonding member 132 of the upper package connected to a second bonding pad (connector right under 132) disposed on the upper surface of the second redistribution substrate to electrically connect the upper package to the second redistribution substrate. See figs. 13a-14 and associated text. With respect to claim 10, Lin et al. teach a package bump (ball right under 156) disposed on a lower surface of the first redistribution substrate. See figs. 13a-14 and associated text. Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20130075924). With respect to claim 11, Lin et al. teach a semiconductor package comprising (see figs. 1-17, particularly figs. 13a-14 and associated text): a first redistribution substrate (connecting structure right under 148); a semiconductor chip 124 disposed on the first redistribution substrate; a chip bump 132 connecting the first redistribution substrate and the semiconductor chip; a second redistribution substrate (connecting structure right over 148); an encapsulant 148 disposed between the first redistribution substrate and the second redistribution substrate and encapsulating the semiconductor chip; a connection structure 250 including a paste (meltable conductive material) bump penetrating the encapsulant and electrically connecting an upper surface of the first redistribution substrate and a lower surface of the second redistribution substrate, wherein at least a portion of the paste bump has a cross-sectional area decreasing in a plan view from an upper portion to a lower portion; and a package bump (ball right under 156) disposed on a lower surface of the first redistribution substrate. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US pub 20130075924) in combination with CN 114649224 (‘224) With respect to claim 12, Lin et al fail to teach the paste bump or meltable bump includes an alloy including tin. CN ‘224 teach using a meltable bump includes an alloy including tin to reduce processing time and negative effects of high temperature processing time. See English text of CN ‘224. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of CN ‘224 into the device of Lin et al. to achieve the above benefit. See English text of CN ‘224. Allowable Subject Matter Claims 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a chip, encapsulant, and a paste bump connection between first and second redistribution substrates as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 28, 2023
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §102, §103
Jun 01, 2026
Interview Requested
Jun 11, 2026
Applicant Interview (Telephonic)
Jun 11, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672565
PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
3y 3m to grant Granted Jun 30, 2026
Patent 12667009
STACKED DIE PACKAGE AND METHODS OF FORMING THE SAME
3y 7m to grant Granted Jun 23, 2026
Patent 12660662
METHODS AND APPARATUS TO ADHERE A DIELECTRIC TO A NONCONDUCTIVE LAYER IN CIRCUIT DEVICES
3y 11m to grant Granted Jun 16, 2026
Patent 12653020
VIA FOR SEMICONDUCTOR DEVICE CONNECTION
2y 2m to grant Granted Jun 09, 2026
Patent 12635524
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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