DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 11/3/25 is acknowledged. Claims 1-18 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 7/28/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the top component with a first width less than that of a second component with a second width (subject matter of claim 10) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “41” has been used to designate both hybrid gate cut structures (see Fig. 1) and a first transistor gate cut (see Fig. 1). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "20" and "30" have both been used to designate a mid-dielectric layer (see e.g., reference numeral 30 is pointing to the mid-dielectric dielectric instead of a hybrid gate cut structure as described in the Specification). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 40. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
In claim 1, lines 2-3 change “a second vertically stacked channel regions” to - -
In claim 18, change “The method of claim 16” to - - The method of claim 17 - - because claim 16 is not a method claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 states in line 4-5, “at least one the first vertically stacked channel region and the second vertically stacked channel region”. This phrasing is unclear as it is missing at least a preposition such as “of the group of” between “at least one” and “the first vertically stacked channel region.” For the purposes of examination, the examiner interprets lines 4-5 in claim 1 as - - at least one of the group of the first vertically stacked channel region and the second vertically stacked channel region - -. However, appropriate correction and/or clarification is requested. Claims 2-11 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1.
Claim 1 introduces “a first vertically stacked channel region” in line 2 but then references “first vertically stacked channel regions” later in the claim. It is unclear if applicant intended the singular or plural form of the first vertically stacked channel region. For the purposes of examination, the examiner interprets “a first vertically stacked channel region” in line 2 as - - s - -. However, appropriate correction and/or clarification is requested. Claims 2-11 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1.
Claim 6 recites the “at least one of the first vertically stacked channel region and the second vertically stacked channel region.” There is a grammatical incongruity between the phrase “at least one of” and the conjunction “and”. As written, it is unclear if the at least one of comprises at least one of the first vertically stacked channel region(s) AND at least one of the second vertically stacked channel region(s). Alternatively, the claim could be interpreted as “at least one of” comprises one or more of the group of the first vertically stacked channel region(s) and the second vertically stacked channel region(s) (i.e., the “at least one of” comprises the first vertically stacked channel region(s) OR the second vertically stacked channel region(s)). Because both interpretations have differing metes and bounds, the claim is rendered indefinite. For the purposes of examination, the examiner interprets the latter interpretation (i.e., the “at least one of” is interpreted as “one or more of the group of...”). However, correction is requested.
Claim 17 states “forming a vertical stack of two field-effect transistors having a gate structure to channel structures of the two field effect transistors” in lines 2-3. It is unclear what is meant by the phrase “gate structure to channel structures” and “of the two field effect transistors” within the context of the rest of the claim. Also, does the gate structure correspond to both or each of the two field-effect transistors or only to at least one of the first-effect transistors?
For the purposes of examination, the examiner interprets “forming a vertical stack of two field-effect transistors having a gate structure to channel structures of the two field effect transistors” as - - forming a vertical stack of two field-effect transistors having a gate structure and channel structures
Claim 18 states “a first field effect transistors for the two field effect transistor” and “a second field effect transistor for the two field effect transistors” in lines 3-4). It is unclear to the examiner what is meant by the phrase “for the two field effect transistor(s)” as used in the claim. For the purposes of examination the interprets the claim as - - The method of claim 17, wherein a mid dielectric layer is positioned in the vertical stack separating channel regions of a first field effect transistor of the two field effect transistor from channel structures of a second field effect transistor of the two field effect transistors, and the first field effect transistor gate cut extends from the first side of the vertical stack to a depth in the vertical stack that is level with the mid dielectric layer, and the second field effect transistor gate cut extends from the second side of the vertical stack to the depth in the vertical stack that is level with the mid dielectric layer - - . However, appropriate correction and/or clarification is requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liebmann et al. (U.S. 2022/0181318 A1; “Liebmann”).
Regarding claim 1, Liebmann discloses a semiconductor device comprising:
A stacked structure including first vertically stacked channel regions (515, Fig. 5) positioned over second vertically stacked channel regions (511, Fig. 5) ([0063]);
At least one gate structure (505, Fig. 5) in electrical communication with at least one of the group of the first vertically stacked channel regions (515, Fig. 5) and the second vertically stacked channel regions (511, Fig. 5) ([0059]); and
At least one two-component gate cut structure (531, 521, Fig. 5) present adjacent to the at least one gate structure (505, Fig. 5), wherein a first component (531, Fig. 5) of the at least one two-component gate cut structure in positioned adjacent to a first [top] portion of the at least one gate structure ([0062]), and a second component (521, Fig. 5) of the at least one two-component gate cut structure is positioned adjacent to a second [bottom] portion of the at least one gate structure ([0061]).
Regarding claim 4, Liebmann discloses the at least one two-component gate cut structure (531, 521, Fig. 5) is present on each (top and bottom) side of the at least one gate structure (505, Fig. 5).
Regarding claim 6, Liebmann discloses channel structures in at least one of the group of the first vertically stacked channel regions (515, Fig. 5) and the second vertically stacked channel regions (511, Fig. 5) are nanosheet semiconductor layers ([0063]).
Claim(s) 1-3, 7-8, 12 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (U.S. 2022/0157815 A1; “Hong”).
Regarding claim 1, Hong discloses a semiconductor device comprising:
A stacked structure including first vertically stacked channel regions (810B, Fig. 8) positioned over second vertically stacked channel regions (810A, Fig. 8) ([0115]);
At least one gate structure (815B, 815A, Fig. 8) in electrical communication with at least one of the group of the first vertically stacked channel regions (810B, Fig. 8) and the second vertically stacked channel regions (810A, Fig. 8) ([0115]); and
At least one two-component gate cut structure (816, Fig. 8) present adjacent to the at least one gate structure (815B, 815A, Fig. 8), wherein a first component (816 adjacent to 815B, Fig. 8) of the at least one two-component gate cut structure in positioned adjacent to a first portion of the at least one gate structure, and a second component (816 adjacent to 815A, Fig. 8) of the at least one two-component gate cut structure is positioned adjacent to a second portion of the at least one gate structure ([0115]).
Regarding claim 2, Hong discloses the first and second vertically stacked channel regions have a mid dielectric layer (806B, Fig. 8) positioned therebetween, wherein the first component (816 adjacent to 815A, Fig. 8) of the at least one two-component gate cut structure is present on a first side of the mid dielectric layer and a second component (816 adjacent to 815A, Fig. 8) of the at least one two-component gate cut structure is present on a second side of the mid dielectric layer.
Regarding claim 3, Hong discloses each of the first (816 adjacent to 815B, Fig. 8) and second (816 adjacent to 815A, Fig. 8) components of the at least one two-component gate cut structure are comprised of at least one dielectric material ([0115]).
Regarding claim 7, Hong discloses a portion of the first component (816 adjacent to 815B, Fig. 8) of the at least one two-component gate cut structure is in direct contact with a second component (816 adjacent to 815A, Fig. 8) of the at least one two-component gate cut structure.
Regarding claim 8, Hong discloses a portion of the first component (816 adjacent to 815B, Fig. 8) of the at least one two-component gate cut structure and a portion of the second component (816 adjacent to 815A, Fig. 8) of the at least one two-component gate cut structure is in direct contact with the mid dielectric layer (806B, Fig. 8).
Regarding claim 12, Hong discloses a semiconductor device comprising:
A first transistor device (transistor comprising 810B, 815B, Fig. 8) stacked over a second transistor device (transistor comprising 810A, 815A, Fig. 8), wherein a mid dielectric (806B, Fig. 8) layer is positioned between the first and second transistor devices ([0115]);
A first transistor side gate cut region (upper 816 adjacent to 815B, Fig. 8) that extends through an entirety of a gate structure (815B, Fig. 8) for the first transistor device to the mid dielectric layer (806B, Fig. 8) ([0115]); and
A second transistor side gate cut region (lower 816 adjacent to 815A, Fig. 8) that that extends through an entirety of a gate structure (815A, Fig. 8) for the second transistor device to the mid dielectric layer (806B, Fig. 8) ([0116]).
Regarding claim 17, Hong discloses a method of forming a semiconductor device comprising:
Forming a vertical stack of two field effect transistors (transistor comprising 810B, 815B and transistor comprising 810A, 815A; Fig. 8) having a gate structure and channel structures ([0115]);
Forming a first field effect transistor gate cut (upper 816 adjacent to 815B, Fig. 8) from a first [top] side of the vertical stack ([0115]); and
Forming a second field effect transistor gate cut (lower 816 adjacent to 815A, Fig. 8) from a second [bottom] side of the vertical stack ([0115]);
Wherein the first [top] and second [bottom] sides of the vertical stack are opposite one another.
Regarding claim 18, Hong discloses a mid dielectric layer (806B, Fig. 8) is positioned in the vertical stack separating channel regions of a first field effect transistor (transistor comprising 810B, 815B, Fig. 8) of the two field effect transistor from channel structures of a second field effect transistor (transistor comprising 810A, 815A, Fig. 8) of the two field effect transistors, and the first field effect transistor gate cut (upper 816 adjacent to 815B, Fig. 8) extends from the first side of the vertical stack to a depth in the vertical stack that is level with the mid dielectric layer, and the second field effect transistor gate cut (lower 816 adjacent to 815A, Fig. 8) extends from the second side of the vertical stack to the depth in the vertical stack that is level with the mid dielectric layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (U.S. 2022/0157815 A1; “Hong”) as applied to claim 1 above, and further in view of Lilak et al. (U.S. 2019/0393214 A1; “Lilak”).
Regarding claim 5, Hong discloses first vertically stacked channel regions (810B, Fig. 8) positioned over second vertically stacked channel regions (810A, Fig. 8) ([0115]) but does not disclose the width of the first vertically stacked channel regions is less than the width of the second vertically stacked channel regions. However, Lilak discloses a width of first vertically stacked channel regions is less than the width of second vertically stacked channel regions (Fig. 2; [0051]-[0055]). This has the advantage of forming multiple transistors of differing size and capabilities. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hong with the width of the first vertically stacked channel regions is less than the width of the second vertically stacked channel regions, as taught by Lilak, so as to forming the multiple transistors having differing sizes and capabilities.
Allowable Subject Matter
Claims 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 1/9/2026