DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAKEUCHI (US 20200161467).
Regarding claim 1, TAKEUCHI discloses a semiconductor device comprising:
a first electrode (fig 8, 15, para 89);
a second electrode (source electrode 14, see fig 5 and 8, para 54 and 122);
a plurality of gate electrodes (gate electrodes 12, see fig 8, para 54) provided between the first and second electrodes (12 are between 15 and 14, see fig 5 and 8, para 122), each of the gate electrodes extending in a first direction (12 extend lengthwise in the x-direction, see fig 8);
a plurality of gate insulation films that covers the plurality of gate electrodes (11, see fig 8, para 53), respectively;
a plurality of first semiconductor regions of a first conductivity type (p-type layers 9 below 7, see fig 8, para 125), each of the first semiconductor regions extending in a second direction orthogonal to the first direction (9 extend lengthwise in the y-direction, see fig 8) below the plurality of gate insulation films (9 extend below 11, see fig 8, para 53);
a plurality of second semiconductor regions of the first conductivity type (p- regions 4a, see fig 8, para 96) that faces the plurality of gate insulation films, respectively, across the plurality of first semiconductor regions (4a faces 11 across 9, see fig 5 and 8);
a plurality of base regions (base regions 7, see fig 8, para 48) provided between the second electrode and the plurality of first semiconductor regions in a third direction orthogonal to the first and second directions (7 is between 9 and the top electrode 14 in the z-direction, see fig 5 and 8, para 48 and 122); and
a plurality of source regions (source regions 8, see fig 8, para 48) provided between the second electrode and the plurality of base regions (8 will be between 7 and 14, see fig 5 and 8, para 122), respectively,
wherein an impurity concentration of the first conductivity type of the plurality of second semiconductor regions is lower than that of the plurality of first semiconductor regions (4a are p- regions and 9 are p regions, see fig 8, para 96 and 128).
Regarding claim 2, TAKEUCHI discloses the semiconductor device according to claim 1, further comprising a plurality of third semiconductor regions (the portions of 3c between each region 9 in the x-direction, see fig 8, 3c, para 95) of a second conductivity type (3c are an n-type region, see fig 8, para 94) that is alternately provided with the plurality of first semiconductor regions in the first direction (the regions of 3c between 9 alternate with 9, which extends into 3c, see fig 8) below the plurality of gate insulation films (3c extends below 11, see fig 8).
Regarding claim 3, TAKEUCHI discloses the semiconductor device according to claim 2, further comprising a plurality of fourth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is alternately provided with the plurality of third semiconductor regions in the second direction (3b and 3a are provided to overlap and alternate along the y-direction, see fig 8, para 94),
wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions (4th region 3b is an n+ region and 3rd region 3c is an n region, see fig 8, para 94).
Regarding claim 4, TAKEUCHI discloses the semiconductor device according to claim 2, wherein the plurality of second semiconductor regions is also provided below the plurality of third semiconductor regions (4a extends to a lower level in the z-direction than does 3c, see fig 8).
Regarding claim 5, TAKEUCHI discloses the semiconductor device according to claim 1, wherein the plurality of second semiconductor regions extends in the first direction along the plurality of gate electrodes (4a extends in the x-direction in parallel with the gate electrode 12, see fig 8).
Regarding claim 6, TAKEUCHI discloses the semiconductor device according to claim 2, further comprising a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions,
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction.
Regarding claim 7, TAKEUCHI discloses the semiconductor device according to claim 2, further comprising:
a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8); and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions (n- region 2, see fig 8, para 41),
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region (second regions 4a extend from fifth regions 3b to sixth region 2, see fig 8).
Regarding claim 8, TAKEUCHI discloses the semiconductor device according to claim 1, further comprising a plurality of third semiconductor regions of a second conductivity type (n-type regions 6 between 9, see fig 8, para 47) that is provided between the plurality of gate insulation films and the plurality of first semiconductor regions (a line can be drawn from 11 to 9 that passes through 6, see fig 8).
Regarding claim 10, TAKEUCHI discloses the semiconductor device according to claim 2, wherein the first conductivity type is a p-type and the second conductivity type is an n-type (the first conductivity type of 9 is p-type and the second conductivity type of 3c is n-type, see fig 8).
Regarding claim 11, TAKEUCHI discloses the semiconductor device according to claim 3, further comprising:
a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8); and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions (n- region 2, see fig 8, para 41),
a SiC substrate provided below the sixth semiconductor region (SiC substrate 1, see fig 8, para 41),
wherein the first electrode is provided on a back surface of the SiC substrate (15 is on a lower surface of 1, see fig 8), the second electrode faces the first electrode in the third direction (14 faces 15 in the z-direction, see fig 5 and 8, para 122), and the second electrode is electrically insulated from the plurality of gate electrodes by plurality of interlayer dielectrics (fig 5 and 8, 13, para 54).
Regarding claim 12, TAKEUCHI discloses a semiconductor device comprising:
a first electrode (fig 8, 15, para 89);
a second electrode (source electrode 14, see fig 5 and 8, para 54 and 122);
a plurality of gate electrodes (gate electrodes 12, see fig 8, para 54) provided between the first and second electrodes (12 are between 15 and 14, see fig 5 and 8, para 122), each of the gate electrodes extending in a first direction (12 extend lengthwise in the x-direction, see fig 8);
a plurality of gate insulation films that covers the plurality of gate electrodes (11, see fig 8, para 53), respectively;
a plurality of first semiconductor regions of a first conductivity type (p-type layers 9 below 7, see fig 8, para 125), each of the first semiconductor regions extending in a second direction orthogonal to the first direction (9 extend lengthwise in the y-direction, see fig 8) below the plurality of gate insulation films (9 extend below 11, see fig 8, para 53);
a plurality of second semiconductor regions of the first conductivity type (p- regions 4a, see fig 8, para 96) that faces the plurality of gate insulation films, respectively, across the plurality of first semiconductor regions (4a faces 11 across 9, see fig 5 and 8); and
a plurality of third semiconductor regions of a second conductivity type (the portions of 3c between each region 9 in the x-direction, see fig 8, 3c, para 95) that is alternately provided with the plurality of first semiconductor regions in the first direction (the regions of 3c between 9 alternate with 9, which extends into 3c, see fig 8) below the plurality of gate insulation films (3c extends below 11, see fig 8), the plurality of third semiconductor regions being spaced apart from each other in the second direction below the plurality of gate insulation films (the plurality of regions 3c are spaced apart in the y-direction, see fig 8),
wherein an impurity concentration of the first conductivity type of the plurality of second semiconductor regions is lower than that of the plurality of first semiconductor regions (4a are p- regions and 9 are p regions, see fig 8, para 96 and 128).
Regarding claim 13, TAKEUCHI discloses the semiconductor device according to claim 12, wherein the plurality of third semiconductor regions is selectively provided below the plurality of gate insulation films (3c are below gate insulator 11, see fig 8, para 95).
Regarding claim 14, TAKEUCHI discloses the semiconductor device according to claim 12, further comprising a plurality of fourth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is alternately provided with the plurality of third semiconductor regions in the second direction (3b and 3a are provided to overlap and alternate along the y-direction, see fig 8, para 94),
wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions (4th region 3b is an n+ region and 3rd region 3c is an n region, see fig 8, para 94).
Regarding claim 15, TAKEUCHI discloses the semiconductor device according to claim 12, wherein the plurality of second semiconductor regions is also provided below the plurality of third semiconductor regions (4a extends to a lower level in the z-direction than does 3c, see fig 8).
Regarding claim 16, TAKEUCHI discloses the semiconductor device according to claim 12, wherein the plurality of second semiconductor regions extends in the first direction along the plurality of gate electrodes (4a extends in the x-direction in parallel with the gate electrode 12, see fig 8).
Regarding claim 17, TAKEUCHI discloses the semiconductor device according to claim 12, further comprising a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8),
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction (3b and 4a alternate in the y-direction, see fig 8).
Regarding claim 18, TAKEUCHI discloses the semiconductor device according to claim 12, further comprising:
a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8),
a sixth semiconductor region of the second conductivity type (n- region 2, see fig 8, para 41) that is provided below the plurality of fifth semiconductor regions (2 is below 3b, see fig 8),
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region (second regions 4a extend from fifth regions 3b to sixth region 2, see fig 8).
Regarding claim 19, TAKEUCHI discloses the semiconductor device according to claim 12, wherein the first conductivity type is a p-type and the second conductivity type is an n-type (the first conductivity type of 9 is p-type and the second conductivity type of 3c is n-type, see fig 8).
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by a different embodiment of TAKEUCHI (US 20200161467).
Regarding claim 1, TAKEUCHI discloses a semiconductor device comprising:
a first electrode (drain electrode 15, see fig 5-6, para 55);
a second electrode (source electrode 14, see fig 5-6, para 54);
a plurality of gate electrodes (gate electrodes 12, see fig 5-6, para 54) provided between the first and second electrodes (12 are between 15 and 14, see fig 5), each of the gate electrodes extending in a first direction (12 extend lengthwise in the x-direction, see fig 5-6);
a plurality of gate insulation films (11, see fig 5-6, para 53) that covers the plurality of gate electrodes, respectively;
a plurality of first semiconductor regions of a first conductivity type (p+ regions 4b, see fig 5-6, para 96), each of the first semiconductor regions extending in a second direction (the regions 4b have an extension in the y-direction, see fig 5-6) orthogonal to the first direction below the plurality of gate insulation films (4b are below 11, see fig 5-6);
a plurality of second semiconductor regions of the first conductivity type (p- regions 4a, see fig 5-6, para 96) that faces the plurality of gate insulation films, respectively, across the plurality of first semiconductor regions (top surfaces of 4a face the bottom surfaces of 10 across 4b, see fig 5-6);
a plurality of base regions (base regions 7, see fig 5-6, para 48) provided between the second electrode and the plurality of first semiconductor regions in a third direction orthogonal to the first and second directions (7 are between 4a and 14 in the vertical z-direction, see fig 5-6); and
a plurality of source regions provided between the second electrode and the plurality of base regions (the plurality of source regions 8, which are between 7 and 14, see fig 5, para 48), respectively,
wherein an impurity concentration of the first conductivity type of the plurality of second semiconductor regions is lower than that of the plurality of first semiconductor regions (first regions 4b are p+ and second regions 4a are p-, see fig 5-6, para 96).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKEUCHI (US 20200161467).
Regarding claim 9, the first embodiment of TAKEUCHI discloses the semiconductor device according to claim 8.
The first embodiment of TAKEUCHI fails to explicitly teach a device, wherein a thickness of the plurality of second semiconductor regions provided below the plurality of third semiconductor regions is greater than that of the plurality of second semiconductor regions provided below the plurality of first semiconductor regions.
Another embodiment of TAKEUCHI discloses a device, wherein a thickness of the plurality of second semiconductor regions provided below the plurality of third semiconductor regions (the thickness of p-region 4 below 6, see fig 3, para 47) is greater than that of the plurality of second semiconductor regions provided below the plurality of first semiconductor regions (the thickness of p-region 4 below 9, which is less than that of 4 below 6 since 9 protrudes below the bottom of 6, see fig 3, para 50).
The two embodiments of TAKEUCHI are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the first embodiment of TAKEUCHI with the second semiconductor region geometry of the second embodiment of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the first embodiment of TAKEUCHI with the second semiconductor region geometry of the second embodiment of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argues that TAKEUCHI does not disclose a device comprising “a plurality of base regions provided between the second electrode and the plurality of first semiconductor regions in a third direction orthogonal to the first and second directions” because in figure 6 of TAKEUCHI, the second semiconductor region 9 extends all the way to the top of the substrate where the second electrode will be (see TAKEUCHI fig 5 and 6). This argument is unpersuasive because a different embodiment of TAKEUCHI in figure 8 discloses a device wherein the second semiconductor region 9 does not extend to the top surface, and is separated from that top surface by the body region 7. Thus, TAKEUCHI does disclose a device comprising “a plurality of base regions provided between the second electrode and the plurality of first semiconductor regions in a third direction orthogonal to the first and second directions” as well as every other element of claim 1, as described in the rejection above.
Regarding claim 12, the applicant argues that TAKEUCHI does not disclose a device wherein “the plurality of third semiconductor regions being spaced apart from each other in the second direction below the plurality of gate insulation films”. This argument is unpersuasive because TAKEUCHI discloses, in figure 8, a device with a plurality of third regions (the n-type regions 3c, see fig 8, para 94) which are spaced apart from each other in the y-direction which is the second direction, and are located under the gate insulators 11. Thus, TAKEUCHI does disclose a device comprising “the plurality of third semiconductor regions being spaced apart from each other in the second direction below the plurality of gate insulation films” as well as every other element of claim 12, as described in the rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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