DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 and 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, line 2 recites “third semiconductor regions of a second conductivity type”. It is not clear, from this limitation, whether or not this second conductivity type is intended to be the same as “a second conductivity type” claimed in claim 1, from which this claim depends, or is a new type. This issue renders the claim indefinite.
Claim 8, line 2 recites “third semiconductor regions of a second conductivity type”. It is not clear, from this limitation, whether or not this second conductivity type is intended to be the same as “a second conductivity type” claimed in claim 1, from which this claim depends, or is a new type. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 8, 10, 12-13, 15-16 and 19-20 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by OKUMURA (US 20190181261).
Regarding claim 1, OKUMURA discloses a semiconductor device comprising:
a first electrode (the lower electrode 15, see figs 1-6, para 66);
a second electrode (the upper electrode 14, see fig 1-6, para 64);
a plurality of gate electrodes (the gate electrodes 10a and 10b, see fig 1-6, para 53) provided between the first and second electrodes, each of the gate electrodes extending in a first direction (10a and b extend in the direction perpendicular to the plane of fig 1, see fig 1-6);
a plurality of gate insulation films (9a and 9b, see fig 1-6, para 52) that covers the plurality of gate electrodes, respectively;
a plurality of first semiconductor regions of a first conductivity type (the n regions of 3 around each gate 10, see fig 1-6, para 49), each of the first semiconductor regions extending in a second direction orthogonal to the first direction below the plurality of gate insulation films (each region of 3 extends in the horizontal direction in fig 1 below some part of 9, see fig 1);
a plurality of second semiconductor regions (regions of 2 below each gate 10 which face upwards towards 10 across 3, see fig 1-6, para 49) of the first conductivity type that faces the plurality of gate insulation films, respectively, across the plurality of first semiconductor regions;
a plurality of base regions (the base regions 6, see fig 1-6, para 50) provided between the second electrode and the plurality of first semiconductor regions in a third direction (the vertical direction in fig 1) orthogonal to the first and second directions;
a plurality of current spreading regions of a second conductive type (p regions 51, 52 and 53, see fig 1-6, para 58) provided between the plurality of base regions and the plurality of first semiconductor regions in the third direction, respectively; and
a plurality of source regions (8, see fig 1-6, para 50) provided between the second electrode and the plurality of base regions, respectively,
wherein an impurity concentration of the first conductivity type of the plurality of second semiconductor regions is lower than that of the plurality of first semiconductor regions (the second regions 2 are n- and the first regions 3 are n, see fig 1).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 1, further comprising a plurality of third semiconductor regions of a second conductivity type (p regions 41a-c, see fig 1-6, para 57) that is alternately provided with the plurality of first semiconductor regions in the first direction below the plurality of gate insulation films (41a alternates with 3 below a portion of 9, see fig 6).
Regarding claim 4, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 2, wherein the plurality of second semiconductor regions is also provided below the plurality of third semiconductor regions (2 is also provided below 41, see fig 1-6).
Regarding claim 5, OKUMURA discloses the semiconductor device according to claim 1, wherein the plurality of second semiconductor regions extends in the first direction along the plurality of gate electrodes (portions of 2 extend in the into the plane direction in fig 1, see fig 6).
Regarding claim 8, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 1, further comprising a plurality of third semiconductor regions of a second conductivity type (p regions 4, see fig 1-6, para 54) that is provided between the plurality of gate insulation films and the plurality of first semiconductor regions (a line can be drawn from 9 to 3 that passes through 4, so 4 is between 9 and 3, see fig 1).
Regarding claim 10, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 2, wherein the first conductivity type is a p-type and the second conductivity type is an n-type (the doping polarity of the device can be reverse, see para 48, such that 2 and 3 would be p-type and 41 would be n-type, see fig 106).
Regarding claim 12, OKUMURA discloses a semiconductor device comprising:
a first electrode (the lower electrode 15, see figs 1-6, para 66);
a second electrode (the upper electrode 14, see fig 1-6, para 64);
a plurality of gate electrodes (the gate electrodes 10a and 10b, see fig 1-6, para 53) provided between the first and second electrodes, each of the gate electrodes extending in a first direction (10a and b extend in the direction perpendicular to the plane of fig 1, see fig 1-6);
a plurality of gate insulation films (9a and 9b, see fig 1-6, para 52) that covers the plurality of gate electrodes, respectively;
a plurality of first semiconductor regions of a first conductivity type (the n regions of 3 around each gate 10, see fig 1-6, para 49), each of the first semiconductor regions extending in a second direction orthogonal to the first direction below the plurality of gate insulation films (each region of 3 extends in the horizontal direction in fig 1 below some part of 9, see fig 1);
a plurality of second semiconductor regions (regions of 2 below each gate 10 which face upwards towards 10 across 3, see fig 1-6, para 49) of the first conductivity type that faces the plurality of gate insulation films, respectively, across the plurality of first semiconductor regions;
a plurality of third semiconductor regions of a second conductivity type (a p-region comprising 41b and 4a, and another p-region comprising 43b and 4b, see fig 1-6, para 56 and 54) that is alternately provided with the plurality of first semiconductor regions in the first direction (41b and 43b alternate with 3 in the first direction, see fig 3 and 6), the plurality of third semiconductor regions being spaced apart from each other in the second direction (4a and 41b are spaced apart from 4b and 43b in the second direction, see fig 3), the plurality of third semiconductor regions being in direct contact with the plurality of gate insulation films (4a and 4b are in direct contact with 9, see fig 1), respectively,
wherein an impurity concentration of the first conductivity type of the plurality of second semiconductor regions is lower than that of the plurality of first semiconductor regions (the second regions 2 are n- and the first regions 3 are n, see fig 1).
Regarding claim 13, OKUMURA discloses the semiconductor device according to claim 12, wherein the plurality of third semiconductor regions is selectively provided below the plurality of gate insulation films (4a and 4b are provided below 9, see fig 1).
Regarding claim 15, OKUMURA discloses the semiconductor device according to claim 12, wherein the plurality of second semiconductor regions is also provided below the plurality of third semiconductor regions (2 is also below 4 and 41, see fig 1).
Regarding claim 16, OKUMURA discloses the semiconductor device according to claim 12, wherein the plurality of second semiconductor regions extends in the first direction along the plurality of gate electrodes (portions of 2 extend in the into the plane direction in fig 1, see fig 6).
Regarding claim 19, OKUMURA discloses the semiconductor device according to claim 12, wherein the first conductivity type is a p-type and the second conductivity type is an n-type (the doping polarity of the device can be reverse, see para 48, such that 2 and 3 would be p-type and 41 would be n-type, see fig 106).
Regarding claim 20, OKUMURA discloses the semiconductor device according to claim 1, wherein in the third direction, the first semiconductor regions (3 are in a layer of the device in the vertical direction, see fig 1), the current spreading regions (51-53 are in a layer of the device in the vertical direction, see fig 1), the base regions (6 are in a layer of the device in the vertical direction, see fig 1), and the source regions (7 are in a layer of the device in the vertical direction, see fig 1) are arranged in layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 6, 7, 9, 11, 14 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA (US 20190181261) in view of TAKEUCHI (US 20200161467).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 2, further comprising a plurality of fourth semiconductor regions of the second conductivity type (fig 1, 4, para 54) that is alternately provided with the plurality of third semiconductor regions in the second direction (41 and 4 alternate along the horizontal direction in fig 1).
OKUMURA fails to explicitly disclose a device wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions.
TAKEUHCI teaches a device wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions (4th region 3b is an n+ region and 3rd region 3c is an n region, see fig 8, para 94).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the doping concentrations of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the doping concentrations of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 6, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 2.
OKUMURA fails to explicitly disclose a device, further comprising a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions,
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction.
TAKEUHCI teaches a device the semiconductor device according to claim 2, further comprising a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions,
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction.
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 2.
OKUMURA fails to explicitly disclose a device, further comprising:
a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions; and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions,
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region.
TAKEUHCI teaches a device, further comprising:
a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8); and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions (n- region 2, see fig 8, para 41),
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region (second regions 4a extend from fifth regions 3b to sixth region 2, see fig 8).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 9, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 8.
OKUMURA fails to explicitly disclose a device, wherein a thickness of the plurality of second semiconductor regions provided below the plurality of third semiconductor regions is greater than that of the plurality of second semiconductor regions provided below the plurality of first semiconductor regions.
TAKEUHCI teaches a device, wherein a thickness of the plurality of second semiconductor regions provided below the plurality of third semiconductor regions (the thickness of p-region 4 below 6, see fig 3, para 47) is greater than that of the plurality of second semiconductor regions provided below the plurality of first semiconductor regions (the thickness of p-region 4 below 9, which is less than that of 4 below 6 since 9 protrudes below the bottom of 6, see fig 3, para 50).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 11, as best as the examiner is able to ascertain the claimed invention, OKUMURA discloses the semiconductor device according to claim 3, further comprising:
a SiC substrate (substrate 1 is below the other doped layers, see fig 1, 1, para 6) provided below the sixth semiconductor region,
wherein the first electrode is provided on a back surface of the SiC substrate (15 is on the bottom surface of 1, see fig 1), the second electrode faces the first electrode in the third direction (14 faces 15 in the vertical direction, see fig 1), and the second electrode is electrically insulated from the plurality of gate electrodes by plurality of interlayer dielectrics (fig 1, 11, para 64).
OKUMURA fails to explicitly disclose a device comprising a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions;
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions.
TAKEUHCI teaches a device comprising a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8); and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions (n- region 2, see fig 8, para 41).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 14, OKUMURA discloses the semiconductor device according to claim 12, further comprising a plurality of fourth semiconductor regions (fig 1-6, 41a, 42a and 43a, see fig 1, para 56) of the second conductivity type that is alternately provided with the plurality of third semiconductor regions in the second direction (41a, 42a and 43a alternate with 4a and 4b in the horizontal direction in fig 1).
OKUMURA fails to explicitly disclose a device wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions.
TAKEUHCI teaches a device wherein an impurity concentration of the second conductivity type of the plurality of fourth semiconductor regions is higher than that of the plurality of third semiconductor regions (4th region 3b is an n+ region and 3rd region 3c is an n region, see fig 8, para 94).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the doping concentrations of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the doping concentrations of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 17, OKUMURA discloses the semiconductor device according to claim 12.
OKUMURA fails to explicitly disclose a device, further comprising a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions,
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction.
TAKEUHCI teaches a device the semiconductor device, further comprising a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8),
wherein the plurality of second semiconductor regions is alternately provided with the plurality of fifth semiconductor regions in the second direction (3b and 4a alternate in the y-direction, see fig 8).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Regarding claim 18, OKUMURA discloses the semiconductor device according to claim 12.
OKUMURA fails to explicitly disclose a device, further comprising:
a plurality of fifth semiconductor regions of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions; and
a sixth semiconductor region of the second conductivity type that is provided below the plurality of fifth semiconductor regions,
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region.
TAKEUHCI teaches a device, further comprising:
a plurality of fifth semiconductor regions (n+ regions 3b, see fig 8, para 94) of the second conductivity type that is provided below the plurality of first semiconductor regions and the plurality of third semiconductor regions (3b extend below 9 and 3c, see fig 8),
a sixth semiconductor region of the second conductivity type (n- region 2, see fig 8, para 41) that is provided below the plurality of fifth semiconductor regions (2 is below 3b, see fig 8),
wherein the plurality of second semiconductor regions extends from the plurality of fifth semiconductor regions up to the sixth semiconductor region (second regions 4a extend from fifth regions 3b to sixth region 2, see fig 8).
OKUMURA and TAKEUCHI are analogous art because they both are directed towards vertical transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OKUMURA with the fifth regions of TAKEUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OKUMURA with the fifth regions of TAKEUCHI in order to increase current path density (see TAKEUCHI para 64).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights