DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/22/2025 with regard to claims 19-20 have been fully considered but they are not persuasive. Applicant argues that the first portion with a circular cross section of Lin cannot be interpreted to have protrusions. However, the examiner maintains that it is reasonable to interpret the first portion protrudes relative to the second portion since it is wider than the second portion and therefore protrudes outward into the encapsulant (48) further than the side surfaces of the second portion (Figure 24). There is no mention in the claims that these protrusions are on or relative to the sidewalls of the first portion. However, in an effort to advance prosecution, newly introduced reference Mun et al. (US Publication No. 2022/0068822) teaches a roughened side surface for a metal pillar. Specifically, Mun discloses protrusions as a textured or roughened sidewall (112) of a metal pillar (111) (Figure 7B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the metal pillar of Lin to include these protrusions, as taught by Mun, since it can suppress interfacial delamination between heterogeneous materials (paragraph 24).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US Publication No. 2019/0103362).
Regarding claim 19, Lin discloses a semiconductor package comprising:
a redistribution substrate (50) comprising a first side (up) and an opposite second side (down)
a plurality of redistribution patterns (54B) in the redistribution substrate (50) and extending in a first direction (horizontal)
a plurality of redistribution vias (60) connected to the plurality of redistribution patterns (54), wherein the plurality of redistribution vias (60) extend toward the second side (68) from a lower side of the plurality of redistribution patterns (54B) in a second direction transverse to the first direction
a semiconductor chip (38) on the first side of the redistribution substrate (50)
a plurality of metal pillars (36) positioned adjacent to a side surface of the semiconductor chip (38), wherein the plurality of metal pillars (36) are connected to the plurality of redistribution patterns (54B), and wherein each metal pillar includes a first portion (36), and a second portion (80)
a plurality of solder balls (70) on the second side of the redistribution substrate (50)
wherein the first portion (36) of each metal pillar has a circular cross-section in plan view, and the second portion (79) of each metal pillar has a square or octagonal cross-section in plan view (paragraph 54; Figure 24)
wherein a side wall of the first portion (36) of each metal pillar comprises protrusions (circular), and a side wall of the second portion of each metal pillar comprises a flat (square) surface (paragraph 54)
wherein a width of the first portion (36) of each metal pillar (36) is different from a width of the second portion (80) of each metal pillar (36)
wherein a height (H2) of the first portion of each metal pillar (36) is greater than a height (D1) of the second portion of each metal pillar (79)
Regarding claim 20, Lin discloses the first portion of each metal pillar has a cylindrical shape in plan view, and a second portion of each metal pillar has a square pillar shape in plan view (paragraph 54).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Publication No. 2019/0103362) in view of Koduri (US Publication No. 2019/0109108).
Regarding claim 1, Lin discloses a semiconductor package comprising:
a redistribution substrate (50) comprising a first side (up) and an opposite second side (down)
a plurality of redistribution patterns (54) in the redistribution substrate (50)
a semiconductor chip (38) on the first side of the redistribution substrate (50)
a plurality of metal pillars (36) positioned around the semiconductor chip (38), wherein the plurality of metal pillars (36) are connected to the plurality of redistribution patterns (54)
a plurality of solder balls (70) on the second side (68) of the redistribution substrate (50)
wherein each of the metal pillars (36) includes a third side facing the first side of the redistribution substrate (50), and an opposite fourth side
wherein the fourth side has a square or octagonal shape in plan view (paragraph 54)
Lin does not disclose the metal pillars to be monolithic with a third side that has a shape different from the fourth side. However, Koduri discloses a monolithic metal pillar with bottom and top cross sections of different shapes (Figure 9D; paragraph 86). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the metal pillars of Lin to be monolithic and formed with different side shapes, as taught by Koduri, since it can improve current density and reduce electromigration and void formation (paragraph 33).
Regarding claim 2, Lin discloses the third side of each metal pillar (36) has a circular shape in plan view (paragraph 54).
Regarding claim 3, Lin discloses each of the plurality of metal pillars (36) comprises a first portion (36), and a second portion (80), and wherein a side wall of the first portion (36) of each metal pillar (36) comprises protrusions (paragraph 54).
Regarding claim 4, Lin discloses a side wall of the second portion (80) of each metal pillar comprises a flat surface (paragraph 54).
Regarding claim 5, Lin discloses a height of the first portion of each metal pillar is greater than a height of the second portion of each metal pillar (paragraphs 47-48; Figure 21).
Regarding claim 6, Lin discloses a ratio of the height of the first portion (H2) of each metal pillar (36) to the height of the second portion (D1) of each metal pillar (79) is 5:1 (paragraph 47; Figure 16).
Regarding claim 7, Lin discloses a width of the first portion (36) of each metal pillar is smaller than a width of the second portion (79) of each metal pillar (Figure 27).
Regarding claim 8, Lin discloses a width of the first portion (36) of each metal pillar is greater than a width of the second portion (79) of each metal pillar (Figure 22).
Regarding claim 9, Lin discloses each of the metal pillars has a height of between 250um and 350um (paragraph 47).
Regarding claim 10, Lin discloses the plurality of redistribution vias (64) connected to the plurality of redistribution patterns (54), wherein the plurality of redistribution vias (64) extend toward the second side (68) of the redistribution substrate (50) in a direction from a lower side of the plurality of redistribution patterns (54).
Regarding claim 11, Lin discloses a semiconductor package comprising:
a redistribution substrate (50) comprising a first side (up) and an opposite second side (down)
a plurality of redistribution patterns (54) in the redistribution substrate (50)
a semiconductor chip (38) on the first side of the redistribution substrate (50)
a plurality of metal pillars (36) positioned adjacent to a side surface of the semiconductor chip (38), wherein the plurality of metal pillars (36) are connected to the plurality of redistribution patterns (54)
a plurality of solder balls (70) on the second side of the redistribution substrate (50)
wherein each of the metal pillars (36) comprises a first portion (36), and a second portion (80)
wherein the first portion (36) of each metal pillar has a cylindrical shape in plan view, and the second portion (79) of each metal pillar has a square shape in plan view (paragraph 54)
Lin does not disclose the metal pillar portions to be formed of the same material. However, Koduri discloses a monolithic metal pillar with bottom and top cross sections of different shapes (Figure 9D; paragraph 86). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the metal pillars of Lin to be monolithic and formed with different side shapes, as taught by Koduri, since it can improve current density and reduce electromigration and void formation (paragraph 33).
Regarding claim 12, Lin discloses each of the plurality of metal pillars (36) comprises a first portion (36) of each metal pillars (36) comprises protrusions (paragraph 54).
Regarding claim 13, Lin discloses a side wall of the second portion (80) of each metal pillar comprises a flat surface (paragraph 54).
Regarding claim 14, Lin discloses a height of the first portion (H2) of each metal pillar (36) is smaller than a width of the second portion of each metal pillar (79) (paragraph 47; Figure 16).
Regarding claim 15, Lin discloses a width of the first portion (36) of each metal pillar is smaller than a width of the second portion (79) of each metal pillar (Figure 27).
Regarding claim 16, Lin discloses a width of the first portion (36) of each metal pillar is greater than a width of the second portion (79) of each metal pillar (Figure 22).
Regarding claim 17, Lin discloses each of the metal pillars has a height of between 250um and 350um (paragraph 47).
Regarding claim 18, Lin discloses the plurality of redistribution vias (64) connected to the plurality of redistribution patterns (54), wherein the plurality of redistribution vias (64) extend toward the second side (68) of the redistribution substrate (50) in a direction from a lower side of the plurality of redistribution patterns (54).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ting et al. (US Publication No. 2023/0129218) discloses roughened protrusions (134) on the side surface of an interconnect (140) (Figure 2E).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/N.R.P/ 4/2/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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