Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment and Request for Reconsideration filed March 18, 2026. Applicant’s amendments to the claims have been entered. Claim 1 has been amended, claim 17 has been added. Claim 2 has been canceled.
Claims 1 and 3-17 are currently pending.
Response to Arguments
Applicant’s amendments and supporting arguments, filed March 18, 2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive in view of Applicant’s amendments to claim 1. Specifically, Applicant persuasively argues on pages 6-8 that:
Koontz does not teach or depict a configuration in which the first semiconductor layer itself includes first and second lateral (parallel) channels that extend to the side wall of the first semiconductor layer and respectively connect to two ends of a groove to provide the claimed external communication and end-to-end flow configuration at the first semiconductor layer. … Koontz does not disclose a structure in which the channel 120 is connected to the external environment through the side wall of the same semiconductor layer in which the groove/channel 120 is formed.
Therefore, the rejections presented in the previous Office Action filed December 23, 2025 have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chainer, US 2017/0186728 A1 (hereinafter Chainer).
Applicant’s arguments with respect to claim(s) 1 and 2-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In response to Applicant’s argument that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claim 1, as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 8, 10, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chainer, US 2017/0186728 A1 (hereinafter Chainer).
Regarding claim 1, as amended, Chainer discloses: A composite substrate, comprising: a first semiconductor layer (Chainer, FIG. 16, die half 1601, [0069]) and a second semiconductor layer (Chainer, FIG. 16, die half 1603, [0069]) that are stacked (Chainer, FIGs. 1 and 16, show die half 1601 [the first semiconductor layer] stacked on die half 1603 [the second semiconductor layer] to form thermal cooling unit 106, [0027; 0069-0070]), wherein at least one heat dissipation groove is disposed on a surface, close to the second semiconductor layer, of the first semiconductor layer (Chainer, FIGs. 1, 3 and 16 show fluid channels 120, including microchannel coolers 120-1 through 120-8, formed in lower surface of die half 1601 [the first semiconductor layer], [0027; 0041]), a heat dissipation channel is disposed on a side wall of the first semiconductor layer (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 and 302-2 [the heat dissipation channel] disposed at outer perimeter, i.e., on the side walls, of die half 1601 [the first semiconductor layer], [0041]), and the heat dissipation channel is in communication with the heat dissipation groove (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 and 302-2 [the heat dissipation channel] connected to, i.e., in communication with microchannel coolers 120-1 through 120-8 [the heat dissipation groove], [0041]), the heat dissipation channel comprises a first channel and a second channel extending in a direction parallel to the first semiconductor layer (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 [the first channel] and 302-2 [the second channel] coplanar with the surface of die half 1601 [the first semiconductor layer], i.e., extending in a direction parallel to the first semiconductor layer]), and the first channel and the second channel extend to the side wall of the first semiconductor layer to communicate with an external environment (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 [the first channel] and 302-2 [the second channel] extend through the side wall of the die half 1601 [the first semiconductor layer] to the external environment) and the first channel and the second channel are respectively in communication with two ends of the heat dissipation groove (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 [the first channel] and 302-2 [the second channel] are respectively in communication with two ends of microchannel coolers 120-1 through 120-8 [the heat dissipation groove], “respective ends of the microchannel coolers 120-1 through 120-8 [the heat dissipation groove] are connected via common fluid channels 304-1 and 304-2 [the first and the second channel],” [0041]).
Regarding claim 3, Chainer discloses: The composite substrate according to claim 1, wherein a shape of a horizontal cross-section of the at least one heat dissipation groove comprises one or a combination of a rectangle (Chainer, FIG. 3 shows a horizontal cross-section of fluid channels 120, including microchannel coolers 120-1 through 120-8 [the heat dissipation groove], is rectangular), semiconductor layer, of the first semiconductor layer (Chainer, “FIG. 3 depicts a top cross-sectional view of the thermal cooling unit 106 of FIG. 1 and FIG. 2, taken along the line A-A shown in FIG. 1 and FIG. 2,” i.e., the horizontal cross-section is parallel to the surface of the die half 1601 [the first semiconductor layer], [0040]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Chainer include one or more of Applicant’s claimed alternative elements, for example: a shape of a horizontal cross-section of the at least one heat dissipation groove comprises a rectangle.
Regarding claim 4, Chainer discloses: The composite substrate according to claim 1, further comprising: a bonding layer located between the first semiconductor layer and the second semiconductor layer (Chainer, FIG. 16, die half 1601 [the first semiconductor layer] bonded together with die half 1603 [the second semiconductor layer] using a copper bond, i.e., a bonding layer, [0027]).
Regarding claim 5, Chainer discloses: The composite substrate according to claim 1, wherein a material of the first semiconductor layer (Chainer, FIG. 16, die half 1601, [0069]) comprises one or a combination of Si (Chainer, [0026-0027]),
Regarding claim 8, Chainer discloses: The composite substrate according to claim 1, wherein a width of the heat dissipation groove is constant, (Chainer, FIGs. 1, 3, and 16, show width of fluid channels 120 [the heat dissipation groove] is constant in a direction from die half 1601 [the first semiconductor layer] to die half 1603 [the second semiconductor layer]).
Regarding claim 10, Chainer discloses: The composite substrate according to claim 1, wherein a material of the second semiconductor layer (Chainer, FIG. 16, die half 1603, [0069]) comprises one or a combination of Si (Chainer, [0026-0027]),
Regarding claim 12, Chainer discloses: The composite substrate according to claim 1, wherein a thickness of the second semiconductor layer is not greater than a thickness of the first semiconductor layer (Chainer, FIG. 16 shows die half 1601 [the first semiconductor layer] and die half 1603 [the second semiconductor layer] having equal thickness, “In the case of 75 μm thick die halves, the cooling unit would have a total thickness of approximately 150 μm,” [0027]).
Regarding claim 13, Chainer discloses: The composite substrate according to claim 1, further comprising: a circulating coolant disposed in the heat dissipation groove (Chainer, fluid channels 120 [the heat dissipation groove] may utilize different types of coolants such as water or a water/propylene glycol mixture, [0072]).
Regarding claim 14, Chainer discloses: The composite substrate according to claim 1, wherein the first semiconductor layer (Chainer, FIGs. 3 and 16, die half 1601, [0069]) comprises a central region (Chainer, FIG. 3, shows central region of die half 1601 [the first semiconductor layer] as the region extending horizontally between the regions of TSVs 116 shown on the left and right edges, [0042]) and an edge region (Chainer, FIG. 3, shows edge region of die half 1601 [the first semiconductor layer] as the regions containing TSVs 116, shown on the left and right edges, excluding the region extending horizontally between TSVs 116 [the central region], [0042]), the at least one heat dissipation groove comprises a plurality of heat dissipation grooves (Chainer, FIG. 3, microchannel coolers 120-1 through 120-8 [the heat dissipation groove], [0041]), and a distribution density of heat dissipation grooves in the central region is greater than a distribution density of heat dissipation grooves in the edge region (Chainer, FIG 3, shows microchannel coolers 120-1 through 120-8 [the heat dissipation groove] only in the region between TSVs 116 [the central region] and not in the region containing TSVs 116 [the edge region], i.e., the distribution density of heat dissipation grooves in the central region is greater than a distribution density of heat dissipation grooves in the edge region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chainer, as applied to claim 1 above, and further in view of Niwa, US 2012/0008655 A1 (hereinafter Niwa).
Regarding claim 6, Chainer teaches nearly every element of claim 6 but is silent regarding: wherein a passivation structure covers on an inner wall of the heat dissipation groove and/or the heat dissipation channel.
However, Niwa, in the same field of endeavor, teaches a microchannel heat sink: wherein a passivation structure (Niwa, FIG. 1, passivation film 6, [0011-0013]) covers on an inner wall of the heat dissipation groove (Niwa, FIG. 1 shows passivation film 6 [the passivation structure] covers on an inner wall of the flow channel 3 [the heat dissipation groove], [0030]) and/or the heat dissipation channel (Niwa, FIG. 1 shows passivation film 6 [the passivation structure] covers on an inner wall of all flow channels 3, including the supply flow channel 3A, the middle flow channel 3B, and the discharge flow channel 3C, [0030]). Niwa teaches that the passivation film is chemically stable and covers the inner-wall surface of the flow channel to prevent corrosion (Niwa, [0011-0015]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chainer with the teachings of Niwa, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Niwa, to prevent corrosion of the cooling channel caused by contact with the coolant, thereby improving device performance and reliability.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chainer as applied to claim 1 above.
Regarding claim 7, Chainer teaches nearly every element of claim 7 but is silent regarding: wherein the first semiconductor layer further comprises a third channel, the at least one heat dissipation groove comprises a plurality of heat dissipation grooves, and the third channel is in communication with the plurality of the heat dissipation grooves.
However, as explained above, regarding claim 1, Chainer teaches a plurality of heat dissipation channels (Chainer, FIG. 3, fluid inlets/outlets 302-1 [the first channel] and 302-2 [the second channel]), a plurality of heat dissipation grooves (Chainer, FIGs. 1, 3 and 16 show fluid channels 120, including microchannel coolers 120-1 through 120-8, formed in lower surface of die half 1601 [the first semiconductor layer]), and also teaches that the plurality of channels are in communication with the plurality of the heat dissipation grooves (Chainer, FIG. 3 shows fluid inlets/outlets 302-1 and 302-2 [the heat dissipation channels] connected to, i.e., in communication with microchannel coolers 120-1 through 120-8 [the heat dissipation grooves], [0041]). Absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed third channel, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chainer as applied to claim 1 above, and further in view of Wan et al., US 2020/0105643 A1 (hereinafter Wan).
Regarding claim 9, Chainer teaches nearly every element of claim 9 but is silent regarding: wherein a width of a shape of a horizontal cross-section of the heat dissipation groove is gradually decreased from a center to two ends, and the horizontal cross-section is parallel to the surface, close to the second semiconductor layer, of the first semiconductor layer.
However, Wan, in the same field of endeavor, teaches an integrated heat spreader with a channel structure designed to dissipate heat from specific locations: wherein a width of a shape of a horizontal cross-section of the heat dissipation groove is gradually decreased from a center to two ends (Wan, FIG. 3a shows width of channel structure 317 [the heat dissipation groove] wider in the center than at the two ends, i.e., gradually decreased from a center to the two ends, “channels of a given channel structure 317 may be wider or otherwise shaped differently to provide distinct flow patterns (suitable for a given application) within that same channel structure 317,” [0030]), and the horizontal cross-section is parallel to the surface, close to the second semiconductor layer, of the first semiconductor layer (Wan, FIG. 3a shows a top-down horizontal cross-section of the shape of channel structures 317 [the heat dissipation groove] parallel to the surface of the heat spreader [analogous to the first semiconductor layer], [0028-0030]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chainer with the teachings of Wan, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Wan, to optimize flow patterns within the cooling channel for a given application, thereby dissipating heat from circuitry at a specific location, thereby improving device performance and reliability.
Regarding claim 17, Chainer teaches nearly every element of claim 9 but is silent regarding: wherein a distance between the heat dissipation grooves in the central region is lower than a distance between the heat dissipation grooves in the edge region.
However, Wan, in the same field of endeavor, teaches an integrated heat spreader configured with separate channel structures and parallel-flow of cooling fluid through those structures, including three distinct channel structures, analogous to Applicant’s claimed heat dissipation grooves in the central region and heat dissipation grooves in the edge region. Wan teaches that the distance between the channels and fins can be configured depending on the given cooling application, and that any number of configurations can be used, “each channel structure 317 can be configured independently of the other channel structures, so that specific cooling needs of corresponding areas of the underlying integrated circuitry can be addressed,” (Wan, [0028-0031]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chainer with the teachings of Wan, insofar as selecting a distance between the heat dissipation grooves in the central region is lower than a distance between the heat dissipation grooves in the edge region, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Wan, to address specific cooling needs of each area of the integrated circuit, thereby improving device performance and reliability.
Claims 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chainer, as applied to claim 1 above, and further in view of Patti et al., US 2020/0243496 A1 (hereinafter Patti).
Regarding claim 11, Chainer teaches nearly every element of claim 11 but is silent regarding: wherein the second semiconductor layer comprises a nitride semiconductor structure, and a surface, away from the first semiconductor layer, of the second semiconductor layer is a Nitrogen-plane.
However, Patti, in the same field of endeavor, teaches a GaN-based HEMT device including: wherein the second semiconductor layer comprises a nitride semiconductor structure (Patti, FIG. 4, GaN-based HEMT device 10 [the nitride semiconductor structure] shown on structural body 3 [analogous to the second semiconductor layer], [0041-0043]). Although Patti is silent regarding a surface of the second semiconductor layer is a Nitrogen-plane, Patti teaches that growth of the crystal lattice of the epitaxial GaN layer is affected by the material interface of the underlying layer (Patti, [0044]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chainer with the teachings of Patti, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. Given the finite number of predictable solutions available to one of ordinary skill in the art when selecting a growth surface for an epitaxial layer, one of ordinary skill would have pursued the known options with a reasonable expectation of success. The motivation for doing so would be, as expressly recognized by Patti, to form a favorable interface between the epitaxially grown nitride semiconductor structure and the underlying surface, thereby improving device performance and reliability.
Regarding claim 16, Chainer teaches nearly every element of claim 16 but is silent regarding: a channel layer and a barrier layer that are sequentially located on the composite substrate; and a source, a gate and a drain that are located on the barrier layer, wherein the source and the drain are respectively located on two sides of the gate.
However, Patti, in the same field of endeavor, teaches a GaN-based HEMT device including: a channel layer (Patti, FIG. 5, channel layer 10b, [0043-0044]) and a barrier layer (Patti, FIG. 5, barrier layer 10c, [0043]) that are sequentially located on the composite substrate (Patti, FIG. 5 shows channel layer 10b and barrier layer 10c stacked sequentially on structural body 3 [analogous to the composite substrate], [0043-0045]); and a source (Patti, FIG. 5, source terminal 10f, [0043-0045]), a gate (Patti, FIG. 5, gate terminal 10e [0043-0045]) and a drain (Patti, FIG. 5, drain terminal 10g, [0043-0045]) that are located on the barrier layer (Patti, FIG. 5 shows source terminal 10f [the source], gate terminal 10e [the gate], and drain terminal 10g [the drain] located on barrier layer 10c [the barrier layer], [0043-0045]), wherein the source and the drain are respectively located on two sides of the gate (Patti, see FIG. 5, “gate terminal 10e [the gate] extends on the barrier layer 10c between a source terminal 10f [the source] and a drain terminal 10g [the drain],” [0043]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the fluid channel heat exchanger taught by Chainer with the high voltage GaN-based HEMT taught by Patti, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Patti, to provide an improved cooling solution for high-voltage power components, thereby improving device performance and reliability.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chainer, as applied to claim 1 above, and further in view of Barlocchi et al., US 2007/0057355 A1 (hereinafter Barlocchi).
Regarding claim 15, Chainer discloses: The composite substrate according to claim 1, wherein a heat dissipation cavity, corresponding to the heat dissipation groove of the first semiconductor layer, is disposed in the second semiconductor layer (Chainer, FIGs. 1 and 16, die half 1603 [the second semiconductor layer] is shown with microchannel coolers 120-1 through 120-8, vertically aligned with, i.e., corresponding to, microchannel coolers 120-1 through 120-8 [the heat dissipation groove] formed in die half 1601 [the first semiconductor layer], [0027]), (Chainer, fluid channels 120, [0027]).
Chainer is silent regarding: the heat dissipation cavity forms a gradually closed top in an epitaxial manner.
However, Barlocchi, in the same field of endeavor, teaches buried microfluidic channels formed by gradually closing the top of the channels by epitaxial growth (Barlocchi, FIG. 16, “the microfluidic channels 115 [analogous to the heat dissipation cavity] are dug in the substrate 102 and are coated by the epitaxial layer 110, which serves as closing layer,” [0049]). FIG. 16 of Barlocchi shows the microfluidic channels 115 [analogous to the heat dissipation cavity] formed with gradually closed tops resulting from epitaxial growth.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chainer with the teachings of Barlocchi, insofar as closing the top of the fluid channel by an epitaxial growth process, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Barlocchi, to simplify the process of forming buried cavities in a semiconductor body, thereby reducing manufacturing costs while improving device performance and reliability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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