DETAILED ACTION
This Office Action is in response to the applicant's amendment filed February 18th, 2026. In virtue of this communication, claims 1-18 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8, 13, 14, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over (US 2004/0080028 A1).
With respect to claim 1, Yanagisawa teaches a clip structure for a packaged semiconductor device in at least Figs. 1-3 and 6, the packaged semiconductor device comprises a first die portion 11a and a second die portion 11c being electrically isolated from the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 39, 41-44, 48), the clip structure comprising:
a first portion 15 being electrically conductive, wherein the first portion 15 is configured to integrally connect a source terminal 18 with the first die portion 11a without an intermediate distinct element between the source terminal 18 and the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 41-44);
a second portion 14 that is electrically conductive and that is integrally formed with the first portion 15 and severed so as to be electrically isolated from the first portion 15, the second portion being configured to connect to a gate terminal 20 (see Figs. 1-3 and 6 and paragraphs 38, 39, 48); and
a gate wire bond 22 configured to connect the second portion with the second die portion 11c (see Figs. 1-3 and 6 and paragraph 48).
The limitation “integrally formed with the first portion and severed so as to be electrically isolated from the first portion” is a product-by-process limitation. The applicant is advised that, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113). In this case, the cited limitation fails to distinguish the claimed structure from the prior art structure of Yanagisawa.
With respect to claim 1, Yanagisawa discloses a clip structure for a packaged semiconductor device in at least Figs. 1-3 and 6, the packaged semiconductor device comprises a first die portion 11a and a second die portion 11c being electrically isolated from the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 39, 41-44, 48), the clip structure comprising:
a first portion 15 being electrically conductive, wherein the first portion 15 is configured to integrally connect a source terminal 18 with the first die portion 11a without an intermediate distinct element between the source terminal 18 and the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 41-44);
a second portion 14 that is electrically conductive and that is electrically isolated from the first portion 15, the second portion being configured to connect to a gate terminal 20 (see Figs. 1-3 and 6 and paragraphs 38, 39, 48); and
a gate wire bond 22 configured to connect the second portion with the second die portion 11c (see Figs. 1-3 and 6 and paragraph 48).
Yanagisawa does not explicitly disclose wherein the second portion 14 is integrally formed with the first portion 15 and severed so as to be electrically isolated from the first portion 15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second portion 14 would be integrally formed with the first portion 15 and severed so as to be electrically isolated from the first portion 15, since it has been held by the courts that patentability of a product does not depend on its method of production. If the product in the product-by-process claim is disclosed, or suggested, by the Prior Art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113).
With respect to claim 2, Yanagisawa teaches the clip structure according to claim 1, wherein the first portion 15 comprises an integrally shaped leadframe providing a single-material electrical conduction channel, configured to integrally connect the source terminal 18 with the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 41-45).
With respect to claim 4, Yanagisawa teaches the clip structure according to claim 1, wherein the gate wire bond 22 extends substantially perpendicularly away from the second die portion 11c over at least a part of the length of the gate wire bond 22 (see Figs. 1-3 and 6 and paragraph 48; note at least a part of 22 has a vertical component, is perpendicular, as it extends from 11c to 14)
With respect to claim 5, Yanagisawa teaches the clip structure according to claim 1, wherein the first portion 15 comprises: a body portion (where 15 connects to 11a) configured to connect with the first die portion 11a; and a finger portion (where 15 extends to 18) comprising a plurality of elongated extensions extending away from the body portion 15 and configured to connect with the source terminal 18 (see Figs. 1-3 and 6 and paragraphs 38, 41-45).
With respect to claim 6, Yanagisawa teaches the clip structure according to claim 1, wherein the second portion 14 comprises an at least partially elongated extension extending away from the second die portion 11c and having an S-shaped lengthwise cross-section configured to bridge a level difference between the gate terminal 20 and the second die portion 11c (see Figs. 1-3 and 6 and paragraphs 38, 39, 48; note S-shape and level difference in Fig. 6).
With respect to claim 8, Yanagisawa teaches the clip structure according to claim 5, wherein each elongated extension of the plurality of elongated extensions has an S-shaped lengthwise cross-section in order to bridge a level difference between the source terminal 18 and the body portion 15 (see Figs. 1-3 and 6 paragraphs 38, 41-45; note S-shape and level difference in Fig. 3).
With respect to claim 13, Yanagisawa teaches a packaged semiconductor device comprising: the first die portion 11a; the second die portion 11c, wherein the second die portion 11c is integrally formed with the first portion 15 and severed to be electrically isolated from the first die portion 11a; and the clip structure according to claim 1, the clip structure having the first portion 15, the second portion 14 and the gate wire bond 22, wherein the clip structure is arranged so that the first portion 15 of the clip structure integrally connects the source terminal 18 with the first die portion 11a and so that the gate wire bond 22 connects the second portion 14 of the clip structure with the second die portion 11c (see Figs. 1-34 and 6 and paragraphs 38, 39, 41-44, 48).
The limitation “integrally formed with the first portion and severed to be electrically isolated from the first portion” is a product-by-process limitation. The applicant is advised that, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113). In this case, the cited limitation fails to distinguish the claimed structure from the prior art structure of Yanagisawa.
With respect to claim 14, Yanagisawa teaches the package semiconductor device of claim 13, wherein the first portion 15 comprises an integrally shaped leadframe providing a single-material electrical conduction channel configured to integrally connect the source terminal 18 with the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 41-45).
With respect to claim 16, Yanagisawa teaches a method of manufacturing the packaged semiconductor device according to claim 13, the method comprising: providing a bottom frame 16; dispensing a first screen (solder) on the bottom frame 16; attaching the first die portion 11a and the second die portion 11c on the first screen (solder); dispensing a second screen (solder) on the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 40, 42, 48, 54. Also see paragraph 51 of applicants original specification which defines first and second screen as an electrically conductive solder; MPEP 2111.01 I); and placing the clip structure having the first portion 15, the second portion 14 and the gate wire bond 22, such that the first portion 15 of the clip structure is placed on the second screen (solder) and the second portion 14 of the clip structure is placed near the second die portion 11c; wherein the step of placing the clip structure comprises a step of disposing the gate wire bond 22 of the clip structure to connect the second portion 14 of the clip structure with the second die portion 11c (see Figs. 1-34 and 6 and paragraphs 38, 39, 41-44, 48).
With respect to claim 17, Yanagisawa teaches the method claim 16, wherein the first portion 15 comprises an integrally shaped leadframe providing a single-material electrical conduction channel configured to integrally connect the source terminal 18 with the first die portion 11a (see Figs. 1-3 and 6 and paragraphs 38, 41-45).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagisawa (US 2004/0080028 A1) in view of Williams et al. (US 6,307,755 B1; hereinafter Williams).
With respect to claim 3, Yanagisawa discloses the clip structure according to claim 1, wherein the gate wire bond comprises a wire thread (see Fig. 6 and paragraph 48; 22 is a wire).
Yanagisawa does disclose wherein the gate wire bond comprises a wire thread having a length of less than 1 mm.
Williams discloses a clip structure wherein a wire bond comprises a wire thread having a length of less than 1 mm (see Table 1 and note max lateral dimension of wire length).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate wire bond of Yanagisawa would comprise a wire thread having a length of less than 1 mm as taught by Williams so as to avoid high wire resistance and sag (see Williams: Table 1).
With respect to claim 15, Yanagisawa discloses the package semiconductor device of claim 13, wherein the gate wire bond comprises a wire thread (see Fig. 6 and paragraph 48; 22 is a wire).
Yanagisawa does disclose wherein the gate wire bond comprises a wire thread having a length of less than 1 mm.
Williams discloses a packaged semiconductor device wherein a wire bond comprises a wire thread having a length of less than 1 mm (see Table 1 and note max lateral dimension of wire length).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate wire bond of Yanagisawa would comprise a wire thread having a length of less than 1 mm as taught by Williams so as to avoid high wire resistance and sag (see Williams: Table 1).
With respect to claim 18, Yanagisawa discloses the method of claim 16, wherein the gate wire bond comprises a wire thread (see Fig. 6 and paragraph 48; 22 is a wire).
Yanagisawa does disclose wherein the gate wire bond comprises a wire thread having a length of less than 1 mm.
Williams discloses a method wherein a wire bond comprises a wire thread having a length of less than 1 mm (see Table 1 and note max lateral dimension of wire length).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate wire bond of Yanagisawa would comprise a wire thread having a length of less than 1 mm as taught by Williams so as to avoid high wire resistance and sag (see Williams: Table 1).
Claims 7 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagisawa (US 2004/0080028 A1) in view of Estacio et al. (US 2019/0393119 A1; hereinafter Estacio).
With respect to claim 7, Yanagisawa discloses the clip structure according to claim 5.
Yanagisawa does not disclose wherein the finger portion comprises at least one arched recess separating neighboring elongated extensions of the plurality of elongated extensions.
Estacio discloses a clip structure in at least Figs. 1-4B wherein a finger portion (between 420) comprises at least one arched recess separating neighboring elongated extensions of the plurality of elongated extensions (at intersection between 420 and 421) (see Figs. 2-4B and paragraphs 25, 27, 29, 32, 34, 37; note arched recess shape at intersection between contact surface and signal leads).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the finger portion of Yanagisawa would comprise at least one arched recess separating neighboring elongated extensions of the plurality of elongated extensions as taught by Estacio as a matter of obvious design choice because it has been held by the courts that a change in shape or configuration, without any criticality, is nothing more than one of numerous shapes that one of ordinary skill in the art will find obvious to provide based on the suitability for the intended final application (see MPEP 2144.04 IV B).
With respect to claim 9, Yanagisawa discloses the clip structure according to claim 6.
Yanagisawa does not disclose wherein the at least partially elongated extension has a hammer-shaped end facing the gate wire bond.
Estacio discloses a clip structure in at least Figs. 1-4B wherein an at least partially elongated extension of (of 450) has a hammer-shaped end facing a gate wire bond 460 (see Figs. 2-4B and paragraphs 25, 29, 34; note hammer-shape of shaded area of signal lead where wire bond is attached).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the at least partially elongated extension of Yanagisawa would have a hammer-shaped end facing the gate wire bond as taught by Estacio so as to provide greater anchoring force between the signal lead and the molding compound (see MPEP 2144 I).
With respect to claim 10, the combination of Yanagisawa and Estacio discloses the clip structure according to claim 7, wherein the at least one arched recess is defined in a region of the finger portion (between 420) adjacent to the body portion of 421 (see Estacio: Figs. 2-4B and paragraphs 25, 27, 29, 32, 34, 37; note arched recess shape at intersection between contact surface and signal leads).
With respect to claim 11, the combination of Yanagisawa and Estacio discloses the clip structure according to claim 7, wherein each elongated extension of the plurality of elongated extensions has an S-shaped lengthwise cross-section configured to bridge a level difference between the source terminal 18 and the body portion 15 (see Yanagisawa: Figs. 1-3 and 6 paragraphs 38, 41-45; note S-shape and level difference in Fig. 3).
With respect to claim 12, the combination of Yanagisawa and Estacio discloses the clip structure according to claim 10, wherein each elongated extension of the plurality of elongated extensions has an S-shaped lengthwise cross-section in order to bridge a level difference between the source terminal 18 and the body portion 15 (see Yanagisawa: Figs. 1-3 and 6 paragraphs 38, 41-45; note S-shape and level difference in Fig. 3).
Response to Arguments
Applicant's arguments filed February 18th, 2026 have been fully considered but they are not persuasive.
The applicant argues that “Yanagisawa fails to disclose ‘a second portion…being integrally formed with the first portion and severed to be electrically isolated from the first portion’ as recited in claim 1”. The examiner respectfully disagrees.
As rejected, the limitation “a second portion…being integrally formed with the first portion and severed to be electrically isolated from the first portion is a product-by-process limitation. The applicant is advised that, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113). In this case, the cited limitation fails to distinguish the claimed structure from the prior art structure of Yanagisawa and the claims remain rejected.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Prior art US 20080036078 A1 discloses a clip structure similar to that of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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