Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-16 without traverse in the reply filed on 11/26/2025 is acknowledged.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites, “wherein the gate-level dielectric layer continuous extends”. The Examiner believes the Applicant intended to write, “wherein the gate-level dielectric layer continuously extends” in order for the claim to be grammatically correct.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al US 20220285344 A1 in view of Mine et al US 20220278209 A1. Chuang et al and Mine et al will be referenced to as Chuang and Mine respectively henceforth.
Regarding Claim 1,
Chuang teaches:
“containing a fin field effect transistor (finFET 104, [0031], FIG. 9B) comprising at least one semiconductor fin (fins 106f, [0027], FIG. 34B: The fins are continuous with the semiconductor substrate. Therefore, the fins comprise a semiconductor material.), and a planar field effect transistor (planar FET, 102, [0031], FIG. 9B);”
Chuang doesn’t substantially teach:
“a logic die comprising a word line switching circuit and a memory die bonded to the logic die , wherein the memory die comprises a three-dimensional memory device. ”
However, Mine teaches:
“a logic die comprising a word line switching circuit and a memory die bonded to the logic die (Mine: [0081], annotated FIG. 14 #1: The memory is formed above the logic die. The may be part of word-line driving circuits.), wherein the memory die comprises a three-dimensional memory device (Mine: [0081]). ”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Chuang is modifiable in view of Mine.
This is because Chuang teaches a planar FET and a FinFET used in a IC comprising a nonvolatile memory device (Chuang: [0023]). Chuang doesn’t substantively teach a planar FET and FinFet used in a three-dimensional NAND memory array. Mine teaches a planar FET and a FinFET used in a IC comprising a nonvolatile memory device (Mine: [0081]: a NAND memory array is a kind of nonvolatile memory.). Mine further teaches a planar FET and FinFet used in a three-dimensional NAND memory array. Because both Chuang and Mine have a planar FET and a FinFET used in a, IC comprising a nonvolatile memory device, one of ordinary skill in the art would have deemed it obvious to substitute the planar FET and FinFET of Chuang into the device of Mine for the predictable result of an IC with a greater lifespan (Chuang: [0026]).
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Mine: annotated FIG. 14 #1
Regarding Claim 2,
Chuang/Mine teaches:
“The semiconductor structure of Claim 1, wherein:
the fin field effect transistor is located in a first device region of the logic die (Chuang: logic core, [0017], FIG. 9B: the logic core region is defined by the presence of FinFET.);
the fin field effect transistor comprises a dielectric isolation layer (Chuang: trench isolation structure 130, [0042], FIG. 9B), wherein the at least one semiconductor fin is laterally surrounded by a first portion of the dielectric isolation layer (Chuang: annotated FIG. 9B #1), at least one first gate dielectric overlying the at least one semiconductor fin (Chuang: second IO dielectric layer 114, [0032], FIG. 35B), a first gate electrode straddling the at least one semiconductor fin (Chuang: gate electrodes 108n, [0073], FIG. 9B), a gate-level dielectric layer laterally surrounding the first gate electrode and having a planar top surface that is coplanar with a top surface of the first gate electrode (Chuang: core dielectric layer 116, [0051], FIG. 9B, annotated FIG. 37B #1);
a planar field effect transistor is located in a second device region of the logic die (Chuang: [0025], FIG. 9B: the planar FET is employed for IO (input-output) purposes.);
the planar field effect transistor comprises an active semiconductor region (Chuang: mesa 106m, N-type device wells 122n, [0027], [0073], FIG. 9B) that is laterally surrounded by a second portion of the dielectric isolation layer (Chuang: annotated FIG. 9B #1), a second gate dielectric overlying a top surface of the active semiconductor region (Chuang: first IO dielectric layer 112, [0092], FIG. 9B), and a second gate electrode overlying the second gate dielectric (Chuang: polysilicon gate electrode 108p, [0102], FIG. 9B); and
the gate-level dielectric layer is not present within the second device region (Chuang: FIG. 9B: 116 is not in the planar devices.). ”
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Annotated FIG. 9B #1
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Annotated FIG. 37B #1
Regarding Claim 3,
Chuang/Mine teaches:
“The semiconductor structure of Claim 2, further comprising a contact-level dielectric layer (Chuang: interconnect dielectric layer 708, CESL 716, [0066-0067], FIG. 9B: The CESL may be silicon nitride. Silicon nitride is a dielectric.) having a first bottom surface contacting a top surface of the second portion of the dielectric isolation layer in the second device region (Chuang: annotated FIG. 9B #1) and having a second bottom surface overlying the gate-level dielectric layer in the first device region (Chuang: annotated FIG. 9B #2). ”
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Annotated FIG. 9B #2
Regarding Claim 4,
Chuang/Mine teaches:
“The semiconductor structure of Claim 3, further comprising a dielectric gate spacer that laterally surrounds the second gate electrode (Chuang: sidewall spacers 120, [0105], FIG. 9B) and having a different material composition than the gate-level dielectric layer (Chuang: [0035-0036]: 116 may be silicon oxide. The sidewall spacers may be silicon nitride. Silicon oxide and silicon nitride are different materials.). ”
Regarding Claim 5,
Chuang/Mine teaches:
“The semiconductor structure of Claim 3, wherein the gate-level dielectric layer continuously extends from each top surface of the at least one first gate dielectric to a top surface of the first portion of the dielectric isolation layer (Chuang: annotated FIG. 37B #2).”
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Annotated FIG. 37B #2
Regarding Claim 6,
Chuang/Mine teaches:
“The semiconductor structure of Claim 3, wherein the gate-level dielectric layer continuous extends from sidewalls of the first gate electrode to a top surface of the first portion of the dielectric isolation layer (Chuang: annotated FIG. 37B #2).”
Regarding Claim 7,
Chuang/Mine teaches:
“The semiconductor structure of Claim 3, wherein an entirety of a dielectric-to-dielectric interface containing the top surface of the second portion of the dielectric isolation layer is an interface between the top surface of the second portion of the dielectric isolation layer and the contact-level dielectric layer (Chuang: annotated FIG. 9B #3: an entirety of a bottom surface of 716 is a dielectric-to-dielectric interface.). ”
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Annotated FIG. 9B #3
Regarding Claim 8,
Chuang/Mine teaches:
“The semiconductor structure of Claim 3, wherein an entirety of the top surface of the second portion of the dielectric isolation layer contacts the first bottom surface of the contact-level dielectric layer (Chuang: annotated FIG. 9B #3). ”
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang/Mine as applied to claims 1-8 above, and further in view of Mizutani et al US 20220399358 A1. Mizutani et al will be referenced to as Mizutani henceforth.
Regarding Claim 16,
Chuang/Mine teaches:
“The semiconductor structure of Claim 2, wherein:
the logic die comprises a logic-side semiconductor substrate (Chuang: semiconductor substrate 106, [0027], FIG. 37B);
the at least one semiconductor fin and the active semiconductor region comprise portions of the logic-side semiconductor substrate (Chuang: [0027]: 106f and 106m are parts of 106.);
the logic die comprises logic-side bonding pads (Mine: various top-level metal line structures 788, annotated FIG. 14 #1: the logic-side bonding pads are a portion of 788.) embedded within logic-side dielectric material layers (Mine: contact-level dielectric layer 70, [0058], FIG. 14 );”
Chuang/Mine doesn’t substantially teach:
“and
the memory die comprises memory-side bonding pads that are embedded within memory-side dielectric material layers and bonded to the logic-side bonding pads.
”
However, Mizutani teaches:
“and
the memory die comprises memory-side bonding pads (Mizutani: memory-side bonding pads 988, [0125], FIG. 17) that are embedded within memory-side dielectric material layers (Mizutani: memory-side dielectric material layers 960, [0115], FIG. 17) and bonded to the logic-side bonding pads (Mizutani: [0125], FIG. 17: The memory-side bonding pads 988 are bonded to the logic-side bonding pads 788.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Chuang/Mine is modifiable in view of Mizutani.
This is because bonding logic-side bonding pads to memory-side bonding pads through metal-to-metal bonding provides the benefit of allowing subsequent high temperature processing on the bonding assembly at processing temperatures above the temperature of solder materials (Mizutani [0125]). One of ordinary skill in the art would recognize this benefit as useful as it gives a designer of a memory chip more options in providing a more effective device such as high temperature metal depositions.
Allowable Subject Matter
Claims 9-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 9,
Chuang/Mine/Mizutani fails to explicitly teach :
“the gate-level dielectric layer comprises at least one source opening overlying each finFET source region” In view of the rest of the limitations of claim 9.
Chuang/Mine/Mizutani fails to explicitly teach the above limitation because the above limitation cannot be found in the prior art of record.
This is because the gate-level dielectric 116 of Chuang does not contain a source opening. The source opening in Chuang lies above the top of the gate electrode which is coplanar with the top of the gate-level dielectric 116. Therefore, the gate-level dielectric cannot comprise a source opening.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Chuang/Mine/Mizutani to reach all of the limitations of the claim.
Regarding Claims 10-15, these claims depend on claim 9 and are objected to for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812