DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Species I-2 (shown in Figs. 13A, 14H, 16, and 20) of Invention I and Claims 1-15 in the response to Restriction Requirements is acknowledged.
Status of Claims
Claims 16-20 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-15 are examined on merits herein.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 15 recites: “logic-side metal interconnect structures embedded in logic-side dielectric material layers and electrically connected to a respective node of the second peripheral circuit”. However, the specification of the application does not teach “a node of the second peripheral circuit” – it teaches nodes only with respect to three-dimensional memory device.
Appropriate correction/clarification is required without introduction of a new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Claim 1 recites (line 6): “in the two-dimensional array”. The recitation is rejected for a lack of antecedent bases, and for this Office Action, it is interpreted as: “in a two-dimensional array”.
In re Claim 12: Lines 5-6 of Claim 12 recite: “the first thin film transistors are electrically connected to the respective electrical node”. There is a lack of antecedent basis for citing: “respective electrical node” - with article “the”, since “respective electrical node” is not cited by lines 1-4 of Claim 12, and is not cited by Claims 9 and 1, on which Claim 12 depends (but cited by Claim 2). In addition, not all first thin film transistors are electrically connected to a same electrical node (as Claim 2 clearly teaches) – some are connected to word lines, while others are connected to drain select transistors of different memory strings.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation is interpreted as: “some of the first thin film transistors are electrically connected to an electrical node”.
In re Claim 14: Lines 3-6 of Claim 14 recite: “a first subset of the memory-side metal interconnect structures is electrically connected to a respective one of the first thin film transistors to the memory-side bonding pads which are embedded in an upper portion of the memory-side dielectric material layers”. The recitation is not clear and appropriate correction is required.
For this Office Action, based on the specification of the application, the cited limitation was interpreted as: “a first subset of the memory-side metal interconnect structures electrically connects a respective one of the first thin film transistors to the memory-side bonding pads which are embedded in an upper portion of the memory-side dielectric material layers”.
In re Claim 15: Claim 15 recites: “logic-side metal interconnect structures embedded in logic-side dielectric material layers and electrically connected to a respective node of the second peripheral circuit”. The recitation is unclear, since the specification of the application does not teach a node with respect to any peripheral circuit – it teaches nodes only with respect to a three-dimensional memory device.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: : “logic-side metal interconnect structures embedded in logic-side dielectric material layers”.
In re Claims 2-11 and 13: Claims 2-11 and 13 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0005544) in view of Park et al. (US 2020/0075577).
In re Claim 1, Chen teaches a semiconductor structure, comprising (Figs. 1A, 10B, 16A/B, and 18F):
a memory die (102 in Figs. 1A and 10B, and a structure incorporating a memory stack 1826 in Fig. 18F, paragraph 0239), comprising:
a three-dimensional memory device (paragraphs 0005, 0070) that comprises an alternating stack of insulating layers 808 and electrically conductive layers 806 (as shown in details in Figs. 8A-8C, paragraph 0095),
memory openings (in which memory strings 208, Figs. 8A-8C, are disposed, paragraph 0094) vertically extending through the alternating stack 806/808, and
memory opening fill structures 812 and 818 (Figs. 8A-8C, paragraph 0096) located in the two-dimensional array of memory openings (inherently existing in the three-dimensional memory array), wherein
each of the memory opening fill structures comprises (Figs. 8A-8C) a respective vertical semiconductor channel 812A (paragraph 0096), a respective drain region (near plug 816, Figs. 8A-8C, paragraph 0096) and a vertical stack of memory elements – comprising portions of memory film 818, Figs. 8A-8C, paragraph 0096) located at levels of the electrically conductive layers 806;
memory-side bonding pads – as bonding contacts in bonding layer 1012 (Fig. 10B, paragraph 0135, and disposed in a bonding interface 1812 of Fig. 18F, paragraph 0250); and
a first peripheral circuit 104 (Figs. 1A, 10B) comprising first transistors 1806, 1804, and unidentified transistors between 1806 and 1804 (Fig. 18F, paragraph 0244) located between the three-dimensional memory device (with stack 1820) and the memory-side bonding pads (within interface 1012 of Fig. 18F); and
a logic die, comprising:
a logic-side substrate 1810 (Fig. 18F, paragraph 0250);
logic-side bonding pads – as bonding pads in layer 1014 (Fig. 10B, paragraph 0135) bonded to the memory-side bonding pads – in layer 1014 (paragraph 0135); and
a second peripheral circuit – as comprising transistors 1816 (Fig. 18F, paragraph 0251).
Chen does not teach that the second peripheral circuit of the logic die is disposed between the logic-side substrate and the logic-side bonding pads, because the logic die is and the first peripheral circuit are bonded to each other on sides of their substrates (see Fig. 18C). However, Chen teaches another disposition of the first peripheral circuit and the logic die: In Fig. 13H, a substrate of a first peripheral circuit 1334/1318 is bonded to a part of the logic die 1322/1328 that is opposite to the logic-die substrate (paragraphs 0192, 0198, 0201).
In view of Fig. 13H, It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen structure of Fig. 18F by substituting a disposition of the logic die and thee first peripheral circuit such that the substrate of the second peripheral circuit would be deposited on the top of the structure, while the logic-side bonding pads would be disposed (for bonding with the first peripheral circuit, as shown in Annotated Modified Fig. 18F)
Annotated Modified Fig. 18F
PNG
media_image1.png
273
403
media_image1.png
Greyscale
on the side of the first peripheral circuit, as shown in a creating by that the second peripheral circuit between the logic-side substrate and the logic-side bonding pads, when it is desirable to have the logic-side substrate on the top of the semiconductor structure.
Chen does not teach, at least, explicitly, that transistors in the first peripheral circuit are thin film transistor.
Park teaches (Fig. 1B, paragraphs 0003, 0030) a thin film transistor (TFT) with a thin semiconductor layer and a back gate 102 having a bottom surface leveled with a bottom surface of a gate dielectric 104.
Chen and Park teach analogous arts directed to transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen device in view of the Park device, since they are from the same field of endeavor, and Park created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the modified Chen structure comprised relative thick transistors in peripheral circuits by substituting its first transistors with first TFTs (per Park), when desirable to have transistors with a higher signal to noise ratio, or with a low power consumption (Park, paragraph 0005). In addition, see MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 9, Chen/Park teaches the semiconductor structure of Claim 1 as cited above, including the first thin film transistors (Fig. 18F and Annotated Fig. 18F of Chen), where a first set of thin film transistors – such as transistors between 1806 and 1804 - is connected, through bit lines (BL), to memory strings (see also Figs. 2 and 7 and paragraphs 0090-0092 and 00113-0114 describing connections between a page buffer 304, bit lines 216 and drains of drain select transistors of memory strings). Chen further teaches (Fig. 18F, Annotated Fig. 18F) a second set of the first thin film transistors – 1804 - which are connected to word lines (electrically conductive layers).
Chen does not explicitly teach that a first subset of the first thin film transistors comprises a respective semiconductor channel including a first semiconductor channel material having a first conductivity type; and a second subset of the first thin film transistors comprises a respective semiconductor channel including a second semiconductor channel material having a second conductivity type. However, Chen uses a CMOS (complementary metal oxide semiconductor) technology in peripheral circuits (paragraph 0082), and, accordingly, he uses N-type transistors and P-type transistors.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first set of TFTs with one type of conductivity and to create the second set of TFTs with a second type of conductivity to enable use of the CMOS technology (Chen, paragraph 0082), and/or realize in the first peripheral circuit at least such structure as a word driver circuit (a portion of which is shown as 308 in Fig. 7 of Chen).
As far as the claims are understood, Claims 2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Nishida et al. (US 2020/0286875).
In re Claim 2, Chen/Park teaches the semiconductor structure of Claim 1 as cited above.
Chen further teaches that the memory die further comprises (Annotated Modified Fig. 18E):
first metal interconnect structures FMI (metal – if made similar to interconnect 1124 in Figs. 11, paragraph 0147) embedded within a first dielectric material layer 1830 (see Fig. 18F showing the number, paragraph 0241) that overlie the three-dimensional memory device (comprising the memory stack 1826) and electrically connected to a respective node (the node being a drain of a top transistor of a memory string, see Fig. 7, paragraphs 0092, 0114 on an electrical connection between a page buffer 702 and a drain of a drain select transistor 212 disposed at a top of a memory openings, as shown in Figs. 8A-8D, through a bit line 216, as explicitly shown in Fig. 2, paragraphs 0092, 0101, the bit line is shown as BL in Annotated Modified Fig. 18F, it shown in a common in the art locations of BL when they are disposed over the memory stack – see Fig. 18A of Nishida, US 2020/0286875, on disposition of a bit line 98, paragraph 0169, on a common knowledge in the art) within the three-dimensional memory device; and
the first thin film transistors 1806 are located over the first dielectric material layer 1830 and electrically connected to a respective electrical node (being conductive lines 806 of the memory stack, as shown in Figs. 8) within the three-dimensional memory device through a respective subset of the first metal interconnect structures -SFMI (as in Annotated Fig. 18F): the cited connections are obvious in view of Fig. 7 showing connections from a word line driver 308 to gates (e.g., word lines, electrical conductive layers) of a memory device 201 (paragraphs 0090, 0115).
Chen/Park does not teach that the first metal interconnect structures are embedded within first dielectric material layers -Chen teaches a single first dielectric material layer.
Nishida teaches (Fig. 18D) first interconnect structures 370, 96, 86 (paragraphs 0168-0170) within first dielectric material layers – 280, 282, 284, 390, etc. (paragraphs 0140, 0166, 0169, 170) that overlie a three-dimensional memory. Nishida also explicitly shows (Fig. 18A) that transistors of a peripheral circuit are connected through a series of interconnect to word lines 246.
Chen/Park and Nishida teach analogous arts directed to a three-dimensional memory device, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Park device in view of the Nishida device since they are from the same field of endeavor, and Nishida created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Park semiconductor structure by substituting a single first dielectric material layer of Chen with a plurality of first dielectric material layers (per Nishida), if such first dielectric material structure is preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 4, Chen/Park/Nishida teaches the semiconductor structure of Claim 2 as cited above, with the first dielectric material layers created, per Nishida, instead of a single dielectric layer 1830 of Chen and with thin film first transistors of Park substituting the first transistors of Chen.
Chen further teaches (Annotated Modified Fig. 18F) a planar dielectric spacer layer – as a part of layer 1808 (paragraph 0245) interposed between the first dielectric material layers 1830 and first thin film transistors 1806, while Park teaches (Fig. 1B) a TFT comprising a first gate dielectric 104 (paragraph 0029) having a planar bottom surface that contacts a horizontal surface of a layer on which the TFT is disposed.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the application, that when first transistors - TFTs of Park - are used in the structures of Claims 1 and 2, there will be no gate electrodes of the first Chen transistors penetrating into dielectric 1808 (as in Fig. 18F), but there will be the gate dielectric of the Park TFTs with a planar bottom surface disposed on, obviously, planar surface of the dielectric spacer layer.
In re Claim 5, Chen/Park/Nishida teaches the semiconductor structure of Claim 4 as cited above, wherein each of the first thin film transistors comprises (Park, Fig. 1B):
a respective first bottom gate electrode 102 (paragraph 0029) - having a bottom surface leveled with a bottom surface of the gate dielectric 104 – and the gate electrode 102 would be obviously in contact with the planar dielectric spacer layer of the Chen/Park/Nishida structure of Claim 2– similar to the gate dielectric, as shown for Claim 4;
a respective first semiconductor channel 106 (paragraph 0030) that overlies the respective first gate dielectric 104;
a respective first source electrode 110 contacting a first end portion of the respective first semiconductor channel 106; and
a respective first drain electrode 112 (paragraph 0030) contacting a second end portion of the respective first semiconductor channel 105.
In re Claim 6, Chen/Park/Nishida teaches the semiconductor structure of Claim 5 as cited above, where in the TFT of Park (Fig. 1B) the first bottom gate electrode 102 is laterally offset from inner edges of the first source electrode 110 and the first drain electrode 112 (paragraph 0030).
As far as the claims are understood, Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park/Nishida in view of Wan (US 2022/0093193).
In re Claim 3, Chen/Park/Nishida teaches the semiconductor structure of Claim 2 as cited above, wherein, as shown for Claim 2 (see also Fig. 18F, Annotated Modified Fig. 18F, and other figures referenced below):
the first peripheral circuit (the lower peripheral circuit, such as 104 in Fig. 1a of Chen) comprises at least one of a word line switching circuit or a word line decoder circuit – it comprising a word driver circuit (as shown for Claim 2);
the first thin film transistors 1806 are electrically connected to a subset of the electrically conductive layers 806 which function as word lines (as shown for Claim 2);
the first metal interconnect structures FMI (as in Annotated Modified Fig. 18F) comprise bit lines BL (216 in Fig. 2, paragraph 0092) that are electrically connected to a respective subset of the drain regions (as shown for Claim 2); and
there are multiple bit lines (216 in Fig. 2 of Chen) and connections to bit lines (from interconnections disposed over BL – see Modified Annotated Fig. 18F).
Nishida further teaches that a plurality of bit lines 98 (Fig. 18D, paragraph 0169) are laterally spaced apart from each other along a first horizontal direction, and it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Park/Nishida of Claim 2 by laterally spacing bit lines apart from each other along the first horizontal direction (per Nishida), in order to enable dispositions of the plurality of bit lines.
Chen/Park/Nishida does not explicitly teach that the second peripheral circuit comprises sense amplifiers that are electrically connected to a respective one of the bit lines. However, Chen and Nishida teach that various control and sensing circuits include a sense amplifier (Chen, paragraph 0082, and Nishida, paragraph 0171), where Chen further teaches that various circuits are embedded within first and second peripheral circuits (paragraph 0082). Since Chen does not explicitly teach which elements are embedded into the first and second peripheral circuit, it would have been obvious for one of ordinary skill in the art before filing the application to dispose the sense amplifier into the second peripheral circuit, in order to enable its disposition into the structure
Wan teaches (paragraph 0037) that both sense amplifiers and page buffers are needed for the memory devices and that they are connected to bit lines.
Chen/Park/Nishida and Wan teach analogous arts directed to semiconductor devices comprised 3D memory circuits, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Park/Nishida device in view of the Wan device, since they are from the same field of endeavor, and Wan created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Chen/Park/Nishida structure by connecting the sense amplifier disposed in the second peripheral circuit to the bit lines, since this connection is needed for operation of the semiconductor structures.
As far as the claims are understood, Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Lupino et al. (US 2022/0216870).
In re Claim 7, Chen/Park teaches the semiconductor structure of Claim 1 as cited above, including the first thin film transistor created per Park.
Park further teaches the first thin film transistor comprising a respective first semiconductor channel 106 (Fig. 1B) created from a metal oxide semiconductor (paragraph 0030), but does not teach that the material includes a non-single-crystalline semiconductor material.
Lupino teaches (paragraph 0002) that it is common creating transistors from amorphous metal oxide semiconductors.
Chen/Park and Lupino teach analogous arts directed to transistors created with metal oxide semiconductors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Park transistor in view of the Lupino teaching of transistors, since they are from the same field of endeavor, and Lupino refers to a successful common practice.
Considering that Park also points out that convential art uses amorphous materials for TFTs (paragraph 0029), it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to also use an amorphous metal oxide semiconductor for the channel of first TFTs in the Chen/Park device, in order to enable the semiconductor part of the TFT and since they are of low cost (Lupino, paragraph 0002).
In re Claim 8, Chen/Park/Lupino teaches the semiconductor structure of Claim 7 as cited above wherein the non-single-crystalline semiconductor material comprises a semiconductor metal oxide material, a semiconductor organic metal halide perovskite material, or a two-dimensional semiconductor material exhibiting higher in-plane electrical conductivity than out-of-plane conductivity – they teach amorphous metal oxide semiconductor.
As far as the claims are understood, Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Rao et al. (CN 10657507).
In re Claim 10, Chen/Park teaches the semiconductor structure of Claim 9 comprising the first subset of TFTs being of a first conductivity type and the second subset of TFT being of a second conductivity type.
Based on the teaching of Chen and Park, one of ordinary skill in the art before the effective date of filing the application would choose the first subset of the first thin film transistors to comprise n-type semiconductor (to enable the first subset of the first transistor), and the first semiconductor channel material would comprise a semiconductor metal oxide material as Park teaches.
Based on the teaching of Chen and Park, one of ordinary skill in the art before the effective date of filing the application would choose the second subset of the first thin film transistors comprises p-type thin film transistors (to enable the second subset of the first transistors), but Chen and Park do not teach such semiconductor as organic metal halide perovskite material.
Rao teaches such semiconductor material as organic metal halide perovskite (Claim 16).
Chen/Park and Rao teach analogous arts directed to semiconductor, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Park structure in view of the Rao teaching, since they are from the same field of endeavor, and Rao’ semiconductor was successfully used in the art.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Park structure of Claim 9 by substituting the metal oxide semiconductor in the second set of the first TFTs for the organic semiconductor metal halide perovskite, if desirable: Based on MPEP 2144.07 Art Recognized Suitability for an Intended Purpose:
As far as the claims are understood, Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Sharma et al. (US 2020/0098880).
In re Claim 11, Chen/Park teaches the semiconductor structure of Claim 9 as cited above, with the first set of TFT comprised a semiconductor of a first conductivity and the second set of TFT comprised a semiconductor of a second conductivity.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first subset of the first thin film transistors comprises n-type thin film transistors and the second subset of the second thin film transistors comprised a p-type conductivity, in order to enable two sets of TFTs comprised semiconductors of different conductivity types.
Chen/Park does not teach such semiconductor channel materials as MoS2 and WS2 – both being two-dimensional semiconductor materials exhibiting higher in-plane electrical conductivity than out-of-plane conductivity: Chen teaches silicon, while Park teaches a metal oxide.
Sharma teaches that materials for channels of transistors may comprise, in addition to silicon and metal oxide, - such two-dimensional (inherently) materials as MoS2 and WS2 (paragraph 0041).
Chen/Park and Sharma teach analogous arts directed to semiconductors used for transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Park structure in view of the Sharma teaching, since they are from the same field of endeavor, and Sharma’ semiconductor was successfully used in the art.
It would have been obvious for one ordinary skill in the art before the effective date of filing the application to modify the Chen/Park TFTs by creating the first subset of TFTs with MoS2 and the second subset of TFTs – with WS2 – instead of metal oxide of Park, if such semiconductor materials are preferred for the manufacturer: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) or Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Although not disclosed by Sharma, MoS2 and WS2 inherently comprise such property as having in-plane electrical conductivity higher than out-of-plane electrical conductivity: See paragraph 0028 of Schmitt et al. (WO 2022147062) – for inherency of the property.
As far as the claims are understood, Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Hosono (US 2005/0018489) and Hou (US 2023/0042438).
In re Claim 12, Chen/Park teaches the semiconductor structure of Claim 9 as cited above including first film transistors and a driver circuit, where first transistors, being TFTs of the first and second conductivities types with source and drain electrodes disposed further from the memory device than their bottom gate electrodes (as shown for Claim 1).
Chen does not teach, at least, explicitly, second metal interconnect structures embedded within second dielectric material layers that overlie the first TFTs and that are electrically connected to respective electrical node (such as to word lines) within the 3D memory device via the second metal interconnect structures and that the dielectric above the first TFTs comprises a plurality of dielectric layers. However, Chen teaches first interconnect structures (under the first TFT) connected to such electrical node as word lines of the 3D memory device, and Chen further teaches (Fig. 10B, paragraph 0142) that a bonding – with interconnect 1012 (which is similar to a bonding interconnect 1812 of Fig. 18F) - between two peripheral circuits - may be created through bonding features disposed in dielectrics adjacent to the interconnects in both peripheral circuits, e.g., there is a dielectric layer above first TFTs 1806, 1804, etc.
Hosono teaches a word lines driver (Fig. 3) comprised a plurality of transistors connected to each other through their source and drain regions (paragraphs 0043-0345), where the driver has a plurality of outputs to word lines (similar to those shown in a portion of driver 308 of Chen’s Fig. 7.
Hou teaches (Fig. 8) that above a peripheral circuit 700 with transistors (CMOS, paragraph 0034) there is dielectric 730 being a plurality of layers of dielectric materials (paragraph 0060).
Chen/Park, Hosono, and Hou teach analogous arts directed either to a word line driver or to a combination of a 3D memory and a peripheral circuit, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying/understanding the Chen/Park structure in view of the Hosono and Hou teachings, since they are from the same field of endeavor, and Hosono and Huo created successfully operated devices.
Since the word line driver needs a plurality of connections between its transistors, where these transistors are some of the first TFTs of the Chen/Park structure, in consideration that source and drive electrodes of the Chen/Park TFTs of Claim 1 are disposed further from the 3D memory than bottom gate electrodes of the TFTs (as shown for Claim 1, and closer to the interface 1812 of Chen’s Fig. 8F), it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Park device of Claim 9 by providing the second dielectric layer above the first TFTs, creating in this layer second metal interconnects for electrical connections between appropriate source/drain electrodes of the first TFTs of the word line driver, as well as from the word line driver to interconnects in the first dielectric layer, and connecting appropriate outputs from the second metal interconnects in the second dielectric layer (above the first transistors) – to respective existing interconnects in the first dielectric layer that are connected to the electrical nodes within the 3D memory, in order to enable operation of the memory structure.
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to substitute a single second dielectric layer of Chen with a plurality of second dielectric layers (per Huo), when interconnects have lines disposed in different dielectric layers (as in the Huo structure).
In re Claim 13, Chen/Park/Hosano/Huo teaches the semiconductor structure of Claim 12 as cited above, including the second metal interconnects located in the second dielectric material layers near the bonding interface 1812 (of Annotated Modified Fig. 18F of Chen).
Chen teaches that the memory die further comprises (Fig. 18F and Annotated Modified Fig. 18F): second thin film transistors 1814, 1816 (paragraph 0251) located over the second metal interconnect structures (not shown in the above figures, but described by Claim 12); and third metal interconnect structures 1818 (paragraph 0253) embedded within third dielectric material layers 1820, 1830 (paragraphs 0253, 0241) overlying the second thin film transistors.
Chen does not explicitly teach that the second thin film transistors are electrically connected to a respective electrical node within the three-dimensional memory device through a respective subset of the third metal interconnect structures, a respective subset of the second metal interconnect structures, and a respective subset of the first metal interconnect structures.
However, Chen explicitly shows (see Annotated Modified Fig. 18F with its explanations appropriate for Claim 9) an electrical connection to between the first interconnect and the bit lines (BL) within the 3D memory device. When a sense amplifier of Chen (connected to BLs, paragraph 0082) is disposed in the second peripheral circuit (and its disposition is a designer choice), it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to make connections from the second set of TFTs through the existing third, second, and third metal interconnects to the 3D memory device.
As far as the claims are understood, Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Park in view of Hosono, Hou, and Noda et al. (US 2001/0013659).
In re Claim 14, Chen/Park teaches the semiconductor structure of Claim 1 as cited above, including the memory-side bonding pads disposed over the first peripheral circuits with first TFTs and the logic die bonded to the memory-side bonding pads.
Chen/Park does not teach, at least, explicitly, that the memory die further comprises memory-side metal interconnect structures embedded within memory-side dielectric material layers that overlie the first thin film transistors, wherein a first subset of the memory-side metal interconnect structures is electrically connected to a respective one of the first thin film transistors to the memory-side bonding pads which are embedded in an upper portion of the memory-side dielectric material layers (e.g., “when a first subset of the memory-side metal interconnect structures electrically connects a respective one of the first thin film transistors to the memory-side bonding pads which are embedded in an upper portion of the memory-side dielectric material layers”, in accordance with the claim interpretation).
However, Chen teaches peripheral circuits comprised a word lines driver 308 (paragraph 0101) a portion of which portion of which is shown in Fig. 7, and also comprised a sense amplifier (paragraph 0082).
Hosono teaches that a word line driver (Fig. 3, paragraphs 0043-0045) comprises a plurality of transistors some of which are connected to a ground, and Noda teaches (paragraph 0125) that a sense amplifier also has connections to the ground.
Chen and Noda teach analogous arts directed to sense amplifiers, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen device in view of the Noda device, since they both are directed to memory devices comprising sense amplifiers, and Noda created a successfully operated device.
Where the first TFT of Claim 1 belong to the word like driver disposed in the first peripheral circuit and the sense amplifier is disposed in the second peripheral circuit, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to connect grounds of the word line driver (e.g., a TFT ground) to the sense amplifier ground through a memory bonding pad, when it is desirable to have their grounds at the same ground potential.
Teaching metal interconnect structures (as shown for Claim 1), Chen/Park (as well as Hosono and Noda) do(es) not explicitly teach that the memory die comprises additional memory-side metal interconnect structures embedded within memory-side dielectric material layers that overlie the first thin film transistors and that one of these additional metal interconnect structures enables the above ground connection. But Chen teaches (Fig. 10B, paragraph 0142) that a bonding structure – with interconnect 1012 (which is similar to a bonding interconnect 1812 of Fig. 18F) - between two peripheral circuits - may be created through bonding features disposed in dielectrics adjacent to the interconnects in both peripheral circuits, e.g., Chen teaches is a dielectric layer above first TFTs 1806, 1804, etc. Since the word line driver (of Hosono) comprises a plurality of interconnected transistors, while the TFTs of Park have source and drain electrodes disposed in a direction of the memory pads, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create a dielectric between the first TFTs and the memory pads and to dispose the additional metal interconnects (including the one connecting grounds of two peripheral circuits) into this dielectric.
Hou teaches (Fig. 8) that above a peripheral circuit 700 with transistors (CMOS, paragraph 0034) there is dielectric 730 being a plurality of layers of dielectric materials (paragraph 0060).
In view of Hou, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to further modify the Chen/Park/Hosono/Noda structure by substituting the additional dielectric above the first TFTs - with the plurality of dielectric material layers, when desirable: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 15, Chen/Park/Hosono/Noda/Huo teaches tyhe semiconductor structure of Claim 14 as cited above wherein, as is obvious from Annotated Modified Fig. 18F and from Fig. 10B, : the logic die further comprises logic-side metal interconnect structures (identified as 1818 in Fig. 18F, paragraph 0253) embedded in logic-side dielectric material layers 1820, 1830 (paragraphs 0241, 0252) and electrically connected to a respective node of the second peripheral circuit (as interpreted); and the logic-side bonding pads 1014 (Fig. 10B) are embedded within the logic-side dielectric material layers (obviously) and electrically connected to the logic-side metal interconnect structures (as shown for Claim 14).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 02/16/26