DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Amendment
Applicant’ amendment filed 06/05/26 has been acknowledged.
Applicant cancelled Claims 17-20, added new Claims 21-25, and amended Claims 1, 12, and 14-15.
Status of Claims
Claims 1-15 and 21-25 are examined on merits herein.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
New Claim 22 recites: “the non-single-crystalline semiconductor channel material comprises amorphous silicon or polysilicon”. Claim 22 depends on Claim 1 that identifies “the non-single-crystalline semiconductor channel” as a channel of thin film transistors of a first peripheral circuit, while the current application does not teach that a channel material of these transistors includes amorphous silicon or polysilicon.
The amendment filed 06/05/26 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
Applicant is required to cancel the new matter in the reply to this Office Action.
Applicant is required to cancel the new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 22-25 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In re Claim 22: New Claim 22 recites: “the non-single-crystalline semiconductor channel material comprises amorphous silicon or polysilicon”. Claim 22 depends on Claim 1 that identifies “the non-single-crystalline semiconductor channel” as a channel of thin film transistors of a first peripheral circuit, while the current application does not teach that a channel material of these transistors includes amorphous silicon or polysilicon. Accordingly, the cited limitation represents a new matter. Appropriate correction is required.
In re Claims 23-25: Claims 23-25 are rejected under 35 U.S.C. 112(a) due to dependency on Claim 22.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 22-25 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 22: New Claim 22 recites: “the non-single-crystalline semiconductor channel material comprises amorphous silicon or polysilicon”. Claim 22 depends on Claim 1 that identifies “the non-single-crystalline semiconductor channel” as a channel of thin film transistors of a first peripheral circuit, while the current application does not teach that a channel material of these transistors includes amorphous silicon or polysilicon – it teaches multiple other materials.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was omitted from consideration.
In re Claims 23-25: Claims 23-25 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 22.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 7-8 are rejected under 35 U.S.C. 112(d).
In re Claim 7: Claim 7 recites: “each of the first thin film transistors comprises a respective first semiconductor channel that includes a non-single-crystalline semiconductor material”. Claim 7 depends on Claim 1, and the amended Claim 1 includes a similar limitation, while Claim 7 does not further limit a limitation of Claim 1: “a first peripheral circuit comprising first thin film transistors comprising a non-single-crystalline semiconductor channel material”. Appropriate correction is required.
In re Claim 8: Claim 8 is rejected under 35 U.S.C. 112(d) due to dependency on Claim 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0005544) in view of Lupino et al. (US 2022/0216870).
In re Claim 1, Chen teaches a semiconductor structure, comprising (Figs. 1A, 10B, 16A/B, and 18F):
a memory die (102 in Figs. 1A and 10B, and a structure incorporating a memory stack 1826 in Fig. 18F, paragraph 0239), comprising:
a three-dimensional memory device (paragraphs 0005, 0070) that comprises an alternating stack of insulating layers 808 and electrically conductive layers 806 (as shown in details in Figs. 8A-8C, paragraph 0095),
memory openings (in which memory strings 208, Figs. 8A-8C, are disposed, paragraph 0094) vertically extending through the alternating stack 806/808, and
memory opening fill structures 812 and 818 (Figs. 8A-8C, paragraph 0096) located in the two-dimensional array of memory openings (inherently existing in the three-dimensional memory array), wherein
each of the memory opening fill structures comprises (Figs. 8A-8C) a respective vertical semiconductor channel 812A (paragraph 0096), a respective drain region (near plug 816, Figs. 8A-8C, paragraph 0096) and a vertical stack of memory elements – comprising portions of memory film 818, Figs. 8A-8C, paragraph 0096) located at levels of the electrically conductive layers 806;
memory-side bonding pads – as bonding contacts in bonding layer 1012 (Fig. 10B, paragraph 0135, that are disposed in a bonding interface 1812 of Fig. 18F, paragraph 0250); and
a first peripheral circuit 104 (Figs. 1A, 10B) comprising first transistors 1806, 1804, and unidentified transistors between 1806 and 1804 (Fig. 18F, paragraph 0244) located between the three-dimensional memory device (with stack 1820) and the memory-side bonding pads (within interface 1012 of Fig. 10B), the first transistors, being planar MOSFETs (like transistors 500), comprise such semiconductor channel material as a single crystalline silicon or it could be any other suitable material (paragraphs 0244 and 0118); and
a logic die, comprising:
a logic-side substrate 1810 (Fig. 18F, paragraph 0250);
logic-side bonding pads – as bonding pads in layer 1014 (Fig. 10B, paragraph 0135) bonded to the memory-side bonding pads – in layer 1014 (paragraph 0135); and
a second peripheral circuit – as comprising transistors 1816 (Fig. 18F, paragraph 0251).
Chen does not teach that the second peripheral circuit of the logic die is disposed between the logic-side substrate and the logic-side bonding pads, because the logic die and the first peripheral circuit are bonded to each other on sides of their substrates (see Fig. 18C). However, Chen teaches another disposition of the first peripheral circuit and the logic die: In Fig. 13H, a substrate of a first peripheral circuit 1334/1318 is bonded to a part of the logic die 1322/1328 that is opposite to the logic-die substrate (paragraphs 0192, 0198, 0201).
In view of Fig. 13H, It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen structure of Fig. 18F by changing dispositions of the logic die and the first peripheral circuit such that the substrate of the second peripheral circuit would be deposited on the top of the structure, while the logic-side bonding pads would be disposed (for bonding with the first peripheral circuit, as shown in Annotated Modified Fig. 18F) on the side of the first peripheral circuit,
Annotated Modified Fig. 18F
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as shown in a creating by that the second peripheral circuit between the logic-side substrate and the logic-side bonding pads, when it is desirable to have the logic-side substrate on the top of the semiconductor structure.
Chen does not teach that transistors in the first peripheral circuit are thin film transistors comprising a non-single-crystalline semiconductor channel material.
Lupino teaches that thin film transistors are fabricated at a temperature less than 450 F, and, accordingly, at low cost (paragraph 0246). Lupino further teaches that these transistors are fabricated with amorphous oxide semiconductors (paragraph 0328).
Chen and Lupino teach analogous arts directed to integrated circuits comprised transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen device in view of the Lupino teaching, since they are from the same field of endeavor, and Lupino created a successfully operated device and referred to a successful practice of using TFT.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the modified Chen structure comprised relative thick transistors in peripheral circuits by substituting its first transistors with first TFTs (per Lupino) which channels comprise amorphous oxide semiconductor, when desirable to reduce a thickness of the structure, to reduce manufacturing cost and avoid damaging of a lower located memory circuits by creating TFT at low temperature (Lupino, paragraph 0246). In addition, see MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 7, Chen/Lupino teaches the semiconductor structure of Claim 1 as cited above and wherein each of the first thin film transistors comprises a respective first semiconductor channel that includes a non-single crystalline semiconductor material.
In re Claim 8, Chen/Lupino teaches the semiconductor structure of Claim 7, wherein the non-single-crystalline semiconductor material comprises a semiconductor metal oxide material (as shown for Claim 1).
In re Claim 9, Chen/Lupino teaches the semiconductor structure of Claim 1 as cited above, including the first thin film transistors (in Fig. 18F and Annotated Fig. 18F of Chen), where a first set of thin film transistors – such as transistors between 1806 and 1804 - is connected, through bit lines (BL), to memory strings (see also Figs. 2 and 7 and paragraphs 0090-0092 and 00113-0114 describing connections between a page buffer 304, bit lines 216 and drains of drain select transistors of memory strings). Chen further teaches (Fig. 18F, Annotated Fig. 18F) a second set of the first thin film transistors – 1804 - which are connected to word lines (electrically conductive layers).
Chen does not explicitly teach that a first subset of the first thin film transistors comprises a respective semiconductor channel including a first semiconductor channel material having a first conductivity type; and a second subset of the first thin film transistors comprises a respective semiconductor channel including a second semiconductor channel material having a second conductivity type. However, Chen uses a CMOS (complementary metal oxide semiconductor) technology in peripheral circuits (paragraph 0082), and, accordingly, he uses N-type transistors and P-type transistors.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first set of TFTs with one type of conductivity and to create the second set of TFTs with a second type of conductivity to enable use of the CMOS technology (Chen, paragraph 0082), and/or realize in the first peripheral circuit at least such structure as a word driver circuit (a portion of which is shown as 308 in Fig. 7 of Chen, and which, as is known in the art, comprises n-type and p-type FETs – see paragraph 0093 of Kim et al., US 2016/0064056, for the common knowledge in the art ).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Lupino in view of Nishida et al. (US 2020/0286875).
In re Claim 2, Chen/Lupino teaches the semiconductor structure of Claim 1 as cited above.
Chen further teaches that the memory die further comprises (Annotated Modified Fig. 18F):
first metal interconnect structures FMI (metal – if made similar to interconnect 1124 in Figs. 11, paragraph 0147) embedded within a first dielectric material layer 1830 (see Fig. 18F showing the number, paragraph 0241) that overlie the three-dimensional memory device (comprising the memory stack 1826) and electrically connected to a respective node (the node being a drain of a top transistor of a memory string, see Fig. 7, paragraphs 0092, 0114 on an electrical connection between a page buffer 702 and a drain of a drain select transistor 212 disposed at a top of a memory openings, as shown in Figs. 8A-8D, through a bit line 216, as explicitly shown in Fig. 2, paragraphs 0092, 0101, the bit line is shown as BL in Annotated Modified Fig. 18F, it shown in a common in the art locations of BL when they are disposed over the memory stack – see Fig. 18A of Nishida, US 2020/0286875, on disposition of a bit line 98, paragraph 0169, on a common knowledge in the art) within the three-dimensional memory device; and
the first thin film transistors 1806 are located over the first dielectric material layer 1830 and electrically connected to a respective electrical node (being conductive lines 806 of the memory stack, as shown in Figs. 8) within the three-dimensional memory device through a respective subset of the first metal interconnect structures -SFMI (as in Annotated Fig. 18F): the cited connections are obvious in view of Fig. 7 showing connections from a word line driver 308 to gates (e.g., word lines, electrical conductive layers) of a memory device 201 (paragraphs 0090, 0115).
Chen/Lupino does not teach that the first metal interconnect structures are embedded within first dielectric material layers - Chen teaches a single first dielectric material layer.
Nishida teaches (Fig. 18D) first interconnect structures 370, 96, 86 (paragraphs 0168-0170) within first dielectric material layers – 280, 282, 284, 390, etc. (paragraphs 0140, 0166, 0169, 170) that overlie a three-dimensional memory. Nishida also explicitly shows (Fig. 18A) that transistors of a peripheral circuit are connected through a series of interconnect to word lines 246.
Chen/Lupino and Nishida teach analogous arts directed to a three-dimensional memory device, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Lupino device in view of the Nishida device since they are from the same field of endeavor, and Nishida created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Lupino semiconductor structure by substituting a single first dielectric material layer of Chen with a plurality of first dielectric material layers (per Nishida), if such first dielectric material structure is preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Lupino/Nishida in view of Park et al. (US 2020/0075577).
In re Claim 4, Chen/Lupino/Nishida teaches the semiconductor structure of Claim 2 as cited above, with the first dielectric material layers created (per Nishida) instead of a single dielectric layer 1830 of Chen and with thin film first transistors of Lupino substituting the first transistors of Chen, each TFT comprising, obviously a gate dielectric layer.
Chen further teaches (Annotated Modified Fig. 18F) a planar dielectric spacer layer – as a part of layer 1808 (paragraph 0245) interposed between the first dielectric material layers 1830 and first thin film transistors 1806.
Lupino, however, does not teach any detail of the thin film transistor, and, accordingly, Chen/Lupino/Nishida does not teach that each of the first thin film transistors comprises such gate dielectric that has a planar bottom surface that contacts a respective segment of a horizontal surface of the planar dielectric spacer layer.
Park teaches (Fig. 1B) a TFT comprising a first gate dielectric 104 (paragraph 0029) having a planar bottom surface that contacts a horizontal surface of a layer on which the TFT is disposed.
Chen/Lupino and Park teach analogous arts directed to transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Lupino TFT in view of the Park TFT, since they are from the same field of endeavor, and Park created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the application, to choose the first TFTs – each having a shape taught by Park, in order to enable such parameter as a transistor shape, and with this modification, when the first transistors/TFT having the shape taught of Park are used in the structures of Claim 2, there will be no gate electrodes of the first Chen transistors penetrating into dielectric 1808 (as in Fig. 18F), but there will be the gate dielectric of the Park TFTs with a planar bottom surface disposed on, obviously, planar surface of the dielectric spacer layer.
In re Claim 5, Chen/Lupino/Nishida/Park teaches the semiconductor structure of Claim 4 as cited above, wherein each of the first thin film transistors comprises (Park, Fig. 1B):
a respective first bottom gate electrode 102 (paragraph 0029) - having a bottom surface leveled with a bottom surface of the gate dielectric 104 – and the gate electrode 102 would be obviously in contact with the planar dielectric spacer layer of the Chen/Park/Nishida structure of Claim 2– similar to the gate dielectric, as shown for Claim 4;
a respective first semiconductor channel 106 (paragraph 0030) that overlies the respective first gate dielectric 104;
a respective first source electrode 110 contacting a first end portion of the respective first semiconductor channel 106; and
a respective first drain electrode 112 (paragraph 0030) contacting a second end portion of the respective first semiconductor channel 105.
In re Claim 6, Chen/Lupino/Nishida/Park teaches the semiconductor structure of Claim 5 as cited above, where in the TFT of Park (Fig. 1B) the first bottom gate electrode 102 is laterally offset from inner edges of the first source electrode 110 and the first drain electrode 112 (paragraph 0030).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Lupino/Nishida in view of Wan (US 2022/0093193).
In re Claim 3, Chen/Lupino/Nishida teaches the semiconductor structure of Claim 2 as cited above, wherein, as shown for Claim 2 (see also Fig. 18F, Annotated Modified Fig. 18F, and other figures referenced below):
the first peripheral circuit (the lower peripheral circuit, such as 104 in Fig. 1a of Chen) comprises at least one of a word line switching circuit or a word line decoder circuit – it comprising a word driver circuit (as shown for Claim 2);
the first thin film transistors 1806 are electrically connected to a subset of the electrically conductive layers 806 which function as word lines (as shown for Claim 2);
the first metal interconnect structures FMI (as in Annotated Modified Fig. 18F) comprise bit lines BL (216 in Fig. 2, paragraph 0092) that are electrically connected to a respective subset of the drain regions (as shown for Claim 2); and
there are multiple bit lines (216 in Fig. 2 of Chen) and connections to bit lines (from interconnections disposed over BL – see Modified Annotated Fig. 18F).
Nishida further teaches that a plurality of bit lines 98 (Fig. 18D, paragraph 0169) are laterally spaced apart from each other along a first horizontal direction, and it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Lupino/Nishida of Claim 2 by laterally spacing bit lines apart from each other along the first horizontal direction (per Nishida), in order to enable dispositions of the plurality of bit lines.
Chen/Lupino/Nishida does not explicitly teach that the second peripheral circuit comprises sense amplifiers that are electrically connected to a respective one of the bit lines. However, Chen and Nishida teach that various control and sensing circuits include a sense amplifier (Chen, paragraph 0082, and Nishida, paragraph 0171), where Chen further teaches that various circuits are embedded within first and second peripheral circuits (paragraph 0082). Since Chen does not explicitly teach which elements are embedded into the first and second peripheral circuit, it would have been obvious for one of ordinary skill in the art before filing the application to dispose the sense amplifier into the second peripheral circuit, in order to enable its disposition into the structure
Wan teaches (paragraph 0037) that both sense amplifiers and page buffers are needed for the memory devices and that they are connected to bit lines.
Chen/Lupino/Nishida and Wan teach analogous arts directed to semiconductor devices comprised 3D memory circuits, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Lupino/Nishida device in view of the Wan device, since they are from the same field of endeavor, and Wan created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Chen/Lupino/Nishida structure by connecting the sense amplifier disposed in the second peripheral circuit to the bit lines, since this connection is needed for operation of the semiconductor structures.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Lupino in view of Rao et al. (CN 10657507).
In re Claim 10, Chen/Lupino teaches the semiconductor structure of Claim 9 comprising the first subset of TFTs being of a first conductivity type and the second subset of TFT being of a second conductivity type.
Based on the teaching of Chen and Lupino, one of ordinary skill in the art before the effective date of filing the application would choose the first subset of the first thin film transistors to comprise n-type semiconductor (to enable the first subset of the first transistor), and the first semiconductor channel material would comprise a semiconductor metal oxide material as Lupino teaches.
Based on the teaching of Chen and Lupino, one of ordinary skill in the art before the effective date of filing the application would choose the second subset of the first thin film transistors comprises p-type thin film transistors (to enable the second subset of the first transistors), but Chen and Lupino do not teach such semiconductor as organic metal halide perovskite material.
Rao teaches such semiconductor material as organic metal halide perovskite (Claim 16).
Chen/Lupino and Rao teach analogous arts directed to semiconductor, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Lupino structure in view of the Rao teaching, since they are from the same field of endeavor, and Rao’ semiconductor was successfully used in the art.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Chen/Lupino structure of Claim 9 by substituting the metal oxide semiconductor in the second set of the first TFTs for the organic semiconductor metal halide perovskite, if desirable: 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945)..See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Lupino in view of Sharma et al. (US 2020/0098880).
In re Claim 11, Chen/Lupino teaches the semiconductor structure of Claim 9 as cited above, with the first set of TFT comprised a semiconductor of a first conductivity and the second set of TFT comprised a semiconductor of a second conductivity.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first subset of the first thin film transistors comprises n-type thin film transistors and the second subset of the second thin film transistors comprised a p-type conductivity, in order to enable two sets of TFTs comprised semiconductors of different conductivity types.
Chen/Lupino does not teach such semiconductor channel materials as MoS2 and WS2 – both being two-dimensional semiconductor materials exhibiting higher in-plane electrical conductivity than out-of-plane conductivity: Chen teaches silicon, while Park teaches a metal oxide.
Sharma teaches that materials for channels of transistors may comprise, in addition to silicon and metal oxide, - such two-dimensional (inherently) materials as MoS2 and WS2 (paragraph 0041).
Chen/Lupino and Sharma teach analogous arts directed to semiconductors used for transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Chen/Lupino structure in view of the Sharma teaching, since they are from the same field of endeavor, and Sharma’ semiconductor was successfully used in the art.
It would have been obvious for one ordinary skill in the art before the effective date of filing the application to modify the Chen/Lupino TFTs by creating the first subset of TFTs with MoS2 and the second subset of TFTs – with WS2 – instead of metal oxide of Park, if such semiconductor materials are preferred for the manufacturer: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) or Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Although not disclosed by Sharma, MoS2 and WS2 inherently comprise such property as having in-plane electrical conductivity higher than out-of-plane electrical conductivity: See paragraph 0028 of Schmitt et al. (WO 2022147062) – for inherency of the property.
Allowable Subject Matter
Claims 12-15 and 21 are viewed as comprising allowable subject matter. The current Office Action objects these claims.
Reason for Identification of Allowable Subject Matter
Re Claim 12: Although there is a combination of prior arts of record that teaches all limitations of Claim 12 (as shown in the Non-Final Rejection mailed 03/06/26), a combination of limitations of Claim 12 (in view of dependency on Claim 9 and 1) is relatively complicated (and needs at least five prior arts for rejection) to render the claim obvious. Claim 12 will be allowed if amended to include all limitations of Claims 1 and 9.
Re Claim 13: Claim 13 depends on Claim 12.
Re Claim 14: Although there is a combination of prior arts of record that teaches all limitations of Claim 14 (as shown in the Non-Final Rejection mailed 03/06/26), a combination of limitations of Claim 14 is relatively complicated (and needs at least five prior arts for rejection) to render the claim obvious. Claim 14 will be allowed if amended to include all limitations of Claims 1.
Re Claim 15: Claim 15 depends on Claim 14.
Re Claim 21: The combination of limitations of Claim 21 (in view of its dependency on Claim 1) is relatively complicated to render the claim obvious. Claim 21 will be allowed if amended to include all limitations of Claim 1.
The prior arts of record include all prior arts cited by the current Office Action and the Non-Final Rejection.
Response to Arguments
Applicant arguments (REMARKS, filed 06/05/26) have been fully considered.
Examiner agrees with the amendments made for Claims 1, 12, 14, and 15 (REMARKS, pages 10-11).
Examiner agrees (REMARKS, page 11) that the amendment to Claim 15 removes previously cited grounds for objection to the specification. However, a set of the amended claims created new grounds for objections to the specification.
Examiner does not agree with the arguments related to allowability of the amended Claim 1 (REMARKS, pages 11-13); the current Office Action shows that the amended Claim 1 is non-patentable. Please, consider that paragraph 0358 of Chen does not view semiconductor layer 1004 as a channel layer – Chen teaches transistors that are in contact with layer 1004, but do not comprise this layer. Regarding transistors in a peripheral circuit, Chen states that their channel may comprise any suitable material. In addition, the current Office Action shows valuable reasons for creating transistors of a peripheral circuit as TFTs comprised a non-single-crystalline semiconductor channel material – such as being manufactured at a low temperature and with a low cost.
Regarding new Claims 21-25 (REMARKS, page 13): It looks like Claims 22-25 contain a new matter (please, see the Office Action).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 07/01/26
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