Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group I, Species A in the reply filed on 1/20/26 is acknowledged. Claim s 6-9 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device/species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/20/26 . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-5 and 10-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Togo (US PGPub 2023/0389317). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Claim 1 : Togo teaches a method, comprising: forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate (Fig. 2) ; forming a first in-process inter-tier dielectric layer (170) over the first alternating stack; forming a first memory opening through the first in-process inter-tier dielectric layer and the first alternating stack (Fig. 3A) ; forming a sacrificial memory opening fill structure in the first memory opening (Fig. 4) ; doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species (Fig. 6)[0147] , wherein a lower portion of the sacrificial memory opening fill structure comprises a sacrificial fill material that is not doped with the at least one dopant species and an upper portion of the sacrificial memory opening fill structure comprises a doped sacrificial fill material that is doped with the atoms of the at least one dopant species [0147] ; forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack (Fig. 7) ; forming a second memory opening through the second alternating stack by performing an anisotropic etch process [0145] that has an etch chemistry to which the doped sacrificial fill material provides a higher etch resistance than the sacrificial fill material (Fig. 9) ; forming a multi-tier memory opening that includes a volume of the second memory opening and a volume of the first memory opening by removing the sacrificial memory opening fill structure (Fig. 17-18) ; forming a memory opening fill structure in the multi-tier memory opening, wherein the memory opening fill structure comprises a vertical semiconductor channel and a vertical stack of memory elements (Fig. 19A-19D) ; and replacing the first sacrificial material layers and the second sacrificial material layers with first electrically conductive layers and second electrically conductive layers, respectively (Fig. 25-26) . Claim 2 : Togo teaches [0147] the doping the upper portion of the first sacrificial memory opening fill structure is performed by implanting ions of the at least one dopant species into the upper portion of the first sacrificial memory opening fill structure. Implanting dopants is well known in the art. Claim 3 : Togo teaches [0147] the implanting ions comprises an unmasked ion implantation process that implants the ions of the at least one first dopant species into an upper portion of the first in-process inter-tier dielectric layer; the first in-process inter-tier dielectric layer is converted into a layer stack including a lower first inter-tier dielectric layer and an upper first inter-tier dielectric layer; the lower first inter-tier dielectric layer is not doped with the ions of the at least one dopant species; and the upper first inter-tier dielectric layer is doped with the ions of the at least one dopant species. Implanting dopants is well known in the art. Claim 4 : Togo teaches [0147] the at least one dopant species comprises noble gas atoms. Claim 5 : Togo teaches [0147] upper first inter-tier dielectric layer comprises a noble gas doped silicon oxide layer, and the doped sacrificial fill material comprises noble gas doped carbon. The first inter-tier dielectric layer would have the same dopants as the doped upper portion of the sacrificial fill due to the doping process being maskless. Claim 10 : Togo teaches [014 5 ] the upper portion of the sacrificial memory opening fill structure functions as an etch stop during the anisotropic etch process. Claim 11 : Togo teaches (Fig. 15) removing the upper portion of the sacrificial memory opening fill structure after forming the second memory opening. Claim 12 : Togo teaches [01 58 ] the upper portion of the sacrificial memory opening fill structure comprises a doped carbon material, and the removing the upper portion of the sacrificial memory opening fill structure comprises performing a timed ashing process. Allowable Subject Matter Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach the regrowing step. Additional references are listed in the PTO-892 that teach claim 1 except the doping of the upper portion of the fill structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SARAH KATE SALERNO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1266 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 6:30am-2:30pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Wael Fahmy can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712721705 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARAH K SALERNO/ Primary Examiner, Art Unit 2814