DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 1/2/2026 is acknowledged.
Applicant amended claims 1, 2, 7, and 13.
Claims 15-20 are rejected with new ground(s) of rejection such that the current office action becomes non-final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sanchez et al. (US 2005/0167782) (hereafter Sanchez).
Regarding claim 1, Sanchez discloses a device comprising:
a first transistor structure (18, 20, 22, and 23 in Fig. 19; and see “transistor” in paragraph 0027) including a gate structure 18 (Fig. 19, paragraph 0013) in a first device layer 28 (Fig. 19, paragraph 0008);
a front-side interconnect structure 33 (Fig. 19, paragraph 0008) on a front-side (top side of 28 in Fig. 19) of the first device layer 28 (Fig. 19);
a first dielectric layer (14 and 31 in Fig. 19, paragraph 0008) on a backside (bottom side of 28 in Fig. 19) of the first device layer 28 (Fig. 19);
a backside via 52 (Fig. 19, paragraph 0016) extending through the first dielectric layer (14 and 31 in Fig. 19) to a source/drain region 22 (Fig. 19, paragraph 0008) of the first transistor structure (18, 20, 22, and 23 in Fig. 19), wherein a lower portion of the backside via 52 (Fig. 19) directly contacts a first sidewall (sidewall of 16 contacting right sidewall of 52 in Fig. 19) of a first semiconductor layer 16 (Fig. 19, paragraph 0007), and wherein the first dielectric layer (14 and 31 in Fig. 19) extends through the first semiconductor layer 16 (Fig. 19).
and wherein the first semiconductor layer 16 (Fig. 19) comprises a second sidewall (sidewall of 16 contacting 31 in Fig. 19) opposite the first sidewall (sidewall of 16 contacting right sidewall of 52 in Fig. 19) and in contact with the first dielectric layer (14 and 31 in Fig. 19), wherein the first sidewall (sidewall of 16 contacting right sidewall of 52 in Fig. 19) is below the gate structure 18 (Fig. 19) and overlapped (see claim filed on 1/2/2026 did not disclose the first sidewall is vertically overlapped by the gate structure such that the first sidewall (sidewall of 16 contacting right sidewall of 52 in Fig. 19) is diagonally overlapped by 18) by the gate structure 18 (Fig. 19).
Regarding claim 4, Sanchez further discloses the device of claim 1, wherein a material of the first semiconductor layer 16 (Fig. 19) and a material of a channel region (region of 16 between 22 and 23 in Fig. 19) of the first transistor structure are the same.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sanchez as applied to claim 1 above, and further in view of Chang et al. (US 2009/0072312) (hereafter Chang).
Regarding claim 2, Sanchez discloses the device of claim 1, however Sanchez does not disclose the second sidewall of the first semiconductor layer forms an angle in a range from 49.7° to about 59.7° with a bottom surface of the first semiconductor layer.
Cheng discloses the second sidewall of the first semiconductor layer 210 (Fig. 6A, paragraph 0008) forms an angle (see θ1 in Fig. 4A and paragraph 0018, wherein “ranges from about 40 degrees to about 70 degrees”) in a range from 49.7° to about 59.7° with a bottom surface of the first semiconductor layer 210 (Fig. 6A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form the second sidewall of the first semiconductor layer forms an angle in a range from 49.7° to about 59.7° with a bottom surface of the first semiconductor layer, as taught by Cheng, since, the volume of strained structure (Cheng, paragraph 0023), tip height, and tip width (surface proximity) etc, may affect the strain effect. In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez as applied to claim 1 above, and further in view of Chang et al. (US 2009/0072312) (hereafter Chang).
Regarding claim 3, Sanchez discloses the device of claim 1, however Sanchez does not disclose the first semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
Chang discloses the first semiconductor layer 16 (Fig. 1F, paragraph 0029, wherein “(100) crystal plane”) comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form the first semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions, as taught by Chang, since, although a (100) crystal orientation (Chang, paragraph 0029) is preferred, the first semiconductor layer 16 (Chang, Fig. 1F, paragraph 0029) may have a (111) crystal plane, (110) crystal plane or other crystal plane. In addition, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a crystal orientation of (100) from the crystal orientations listed in paragraph 0029 of Chang (e.g. (100) , (111), or (110)); if this leads to the anticipated success, in the instant case providing a crystal orientation to SOI layer, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 6, Sanchez discloses the device of claim 1, however Sanchez does not disclose the first semiconductor layer has a height that is in a range from about 6 nm to about 7 nm.
Chang discloses the first semiconductor layer 16 (Fig. 1F, paragraph 0030, wherein “about 5 nm to about 100 nm”) has a height that is in a range from about 6 nm to about 7 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form the first semiconductor layer has a height that being in a range from about 6 nm to about 7 nm, as taught by Chang, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sanchez as applied to claim 4 above, and further in view of Cai et al. (US 2013/0154029) (hereafter Cai).
Regarding claim 5, Sanchez further discloses the device of claim 4, wherein a first portion of the source/drain region 22 (Fig. 19, paragraph 0024) contacts the channel region (region of 16 between 22 and 23 in Fig. 19).
Sanchez does not disclose a first width of the first portion of the source/drain region is larger than a second width of a top surface of the source/drain region and a third width of a bottom surface of the source/drain region.
Cai discloses a first width of the first portion (longest horizontal portion of 1202 in Fig. 12) of the source/drain region 1202 (Fig. 12, paragraph 0040) is larger than a second width of a top surface (top surface of 1202 in Fig. 12) of the source/drain region 1202 (Fig. 12, paragraph 0040) and a third width of a bottom surface (bottom surface of 1202 in Fig. 12) of the source/drain region 1202 (Fig. 12, paragraph 0040).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form a first width of the first portion of the source/drain region is larger than a second width of a top surface of the source/drain region and a third width of a bottom surface of the source/drain region, as taught by Cai, since its proximity to the channel region (Cai, paragraph 0044) in the angled indentations of the recessed portion 1006 (Cai, Fig. 11, paragraph 0044), the stressor 1202 (Cai, Fig. 12, paragraph 0044) can more effectively impose a stress on the channel region 802 (Cai, Fig. 12, paragraph 0044) to enhance charge carrier mobility in the channel region 802 (Cai, Fig. 12, paragraph 0044).
Claims 7, 9, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez et al. (US 2005/0167782) (hereafter Sanchez), in view of Cheng et al. (US 2013/0119444) (hereafter Cheng).
Regarding claim 7, Sanchez discloses a device comprising:
a first interconnect structure 33 (Fig. 19, paragraph 0009) comprising conductive lines (see paragraph 0008, wherein “A drain contact 33 makes electrical connection to the drain region 23”);
a second interconnect structure (68 and 99 in Fig. 19, paragraph 0030) comprising a backside power rail (see paragraph 0030, wherein “conductive material 68 may be implemented as an efficient power plane across a semiconductor die to distribute a power supply voltage across the semiconductor device 10”);
a device layer (28, 30, 18, 20, 22, and 23 in Fig. 19) between the first interconnect structure 33 (Fig. 19) and the second interconnect structure 52 (Fig. 19), the device layer (28, 30, 18, 20, 22, and 23 in Fig. 19) comprising a transistor (18, 20, 22, and 23 in Fig. 19; and see “transistor” in paragraph 0027);
a first dielectric layer 14 (Fig. 19, paragraph 0008) disposed between the device layer 28 (Fig. 19) and the second interconnect structure 52 (Fig. 19);
a semiconductor layer 16 (Fig. 19, paragraph 0007) disposed between the device layer (28, 30, 18, 20, 22, and 23 in Fig. 19) and portions of the first dielectric layer 14 (Fig. 19); and
a conductive via 52 (Fig. 19, paragraph 0008) extending through the semiconductor layer 16 (Fig. 19) and the first dielectric layer 14 (Fig. 19), wherein the conductive via 52 (Fig. 19) electrically connects a source/drain region 22 (Fig. 19, paragraph 0008) of the transistor to the backside power rail (68 and 99 in Fig. 19; and see paragraph 0030).
Sanchez does not disclose the semiconductor layer comprises a taper sidewall that is adjacent to the first dielectric layer.
Cheng discloses the semiconductor layer 210 (Fig. 6A, paragraph 0008) comprises a taper sidewall (see θ1 in Fig. 4A and paragraph 0018, wherein “ranges from about 40 degrees to about 70 degrees”) that is adjacent to the first dielectric layer (insulator portion of “semiconductor on insulator (SOI)” in paragraph 0008)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form the semiconductor layer comprises a taper sidewall that is adjacent to the first dielectric layer, as taught by Cheng, since, the volume of strained structure (Cheng, paragraph 0023), tip height, and tip width (surface proximity) etc, may affect the strain effect.
Regarding claim 9, Sanchez in view of Cheng discloses the device of claim 8, however Sanchez does not disclose a sidewall of the semiconductor layer forms an angle in a range from 49.7° to 59.7° with a bottom surface of the semiconductor layer.
Cheng discloses a sidewall of the semiconductor layer 210 (Fig. 6A, paragraph 0008) forms an angle (see θ1 in Fig. 4A and paragraph 0018, wherein “ranges from about 40 degrees to about 70 degrees”) in a range from 49.7° to 59.7° with a bottom surface of the semiconductor layer 210 (Fig. 6A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form a sidewall of the semiconductor layer forms an angle in a range from 49.7° to 59.7° with a bottom surface of the semiconductor layer, as taught by Cheng, since, the volume of strained structure (Cheng, paragraph 0023), tip height, and tip width (surface proximity) etc, may affect the strain effect. In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Sanchez further discloses the device of claim 7, wherein a first portion of the conductive via 52 (Fig. 19) that extends through the semiconductor layer 16 (Fig. 19) has a larger width (see Fig. 19, wherein vertical length of 52 is larger than vertical length of 16) than a second portion of the semiconductor layer 16 (Fig. 19) that extends through the first dielectric layer 14 (Fig. 19).
Regarding claim 15, Sanchez discloses a device comprising:
a device layer (28, 30, 18, 20, 22, and 23 in Fig. 19) comprising a first transistor structure (18, 20, 22, and 23 in Fig. 19; and see “transistor” in paragraph 0027), wherein the first transistor structure (18, 20, 22, and 23 in Fig. 19) comprises:
a first source/drain region 22 (Fig. 19, paragraph 0008) and a second source/drain region 23 (Fig. 19, paragraph 0008); and
a channel region (portion of 16 between 22 and 23 in Fig. 19) disposed between the first source/drain region 22 (Fig. 19) and the second source/drain region 23 (Fig. 19);
a first dielectric layer 14 (Fig. 19, paragraph 0008) on a backside of the device layer (28, 30, 18, 20, 22, and 23 in Fig. 19);
a first semiconductor layer (lower portion of 16 in Fig. 19, paragraph 0007) disposed between the device layer (28, 30, 18, 20, 22, and 23 in Fig. 19) and portions of the first dielectric layer 14 (Fig. 19); and
a backside via 52 (Fig. 19, paragraph 0008) extending through the first dielectric layer 14 (Fig. 19) and the first semiconductor layer (lower portion of 16 in Fig. 19), the backside via 52 (Fig. 19) being in physical contact with the first source/drain region 22 (Fig. 19).
Sanchez does not disclose a sidewall of the first semiconductor layer forms an angle that is in a range from 49.7° to 59.7° with a bottom surface of the first semiconductor layer.
Cheng discloses a sidewall of the first semiconductor layer 210 (Fig. 6A, paragraph 0008) forms an angle (see θ1 in Fig. 4A and paragraph 0018, wherein “ranges from about 40 degrees to about 70 degrees”) that is in a range from 49.7° to 59.7° with a bottom surface of the first semiconductor layer 210 (Fig. 6A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form a sidewall of the first semiconductor layer forms an angle that is in a range from 49.7° to 59.7° with a bottom surface of the first semiconductor layer, as taught by Cheng, since, the volume of strained structure (Cheng, paragraph 0023), tip height, and tip width (surface proximity) etc, may affect the strain effect. In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 16, Sanchez further discloses the device of claim 15, further comprising: a backside power rail (68, 54, and 32 in Fig. 19; and see paragraph 0030, wherein “conductive material 68 may be implemented as an efficient power plane across a semiconductor die to distribute a power supply voltage across the semiconductor device 10”) over the first dielectric layer 14 (Fig. 19) and the backside via 52 (Fig. 19), wherein the backside power rail (68, 54, and 32 in Fig. 19) is electrically coupled to the first source/drain region 22 (Fig. 19) through the backside via 52 (Fig. 19).
Claims 8, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez in view of Cheng as applied to claims 7 and 15 above, and further in view of Chang et al. (US 2009/0072312) (hereafter Chang).
Regarding claim 8, Sanchez in view of Cheng discloses the device of claim 7, however Sanchez and Cheng do not disclose the semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
Chang discloses the semiconductor layer 16 (Fig. 1F, paragraph 0029, wherein “(100) crystal plane”) comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form the semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions, as taught by Chang, since, although a (100) crystal orientation (Chang, paragraph 0029) is preferred, the first semiconductor layer 16 (Chang, Fig. 1F, paragraph 0029) may have a (111) crystal plane, (110) crystal plane or other crystal plane. In addition, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a crystal orientation of (100) from the crystal orientations listed in paragraph 0029 of Chang (e.g. (100) , (111), or (110)); if this leads to the anticipated success, in the instant case providing a crystal orientation to SOI layer, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 10, Sanchez in view of Cheng discloses the device of claim 7, however Sanchez and Cheng do not disclose the semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
Chang discloses the semiconductor layer 16 (Fig. 1F, paragraph 0029, wherein “(100) crystal plane”) comprises silicon having a crystal orientation that is in a <110> family of crystal directions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form the semiconductor layer comprises silicon having a crystal orientation that is in a <110> family of crystal directions, as taught by Chang, since, although a (100) crystal orientation (Chang, paragraph 0029) is preferred, the first semiconductor layer 16 (Chang, Fig. 1F, paragraph 0029) may have a (111) crystal plane, (110) crystal plane or other crystal plane. In addition, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a crystal orientation of (100) from the crystal orientations listed in paragraph 0029 of Chang (e.g. (100) , (111), or (110)); if this leads to the anticipated success, in the instant case providing a crystal orientation to SOI layer, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 19, Sanchez in view of Cheng discloses the device of claim 15, however Sanchez and Cheng do not disclose the first semiconductor layer has a height that is in a range from 6 nm to 7 nm.
Chang discloses the first semiconductor layer 16 (Fig. 1F, paragraph 0030, wherein “about 5 nm to about 100 nm”) has a height that is in a range from about 6 nm to about 7 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez to form the first semiconductor layer has a height that being in a range from about 6 nm to about 7 nm, as taught by Chang, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 11, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez in view of Cheng as applied to claims 7 and 15 above, and further in view of Yokoyama et al. (US 2015/0061020) (hereafter Yokoyama).
Regarding claim 11, Sanchez in view of Cheng discloses the device of claim 7, however Sanchez and Cheng do not disclose a dielectric liner disposed between the first dielectric layer and the semiconductor layer, and between the conductive via and the first dielectric layer.
Yokoyama discloses a dielectric liner 61 (Fig. 1A, paragraph 0064) disposed between the first dielectric layer 63 (Fig. 1A, paragraph 0064) and the semiconductor layer 10 (Fig. 1A, paragraph 0055), and between the conductive via (P in Fig. 1A, paragraph 0057) and the first dielectric layer 63 (Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form a dielectric liner disposed between the first dielectric layer and the semiconductor layer, and between the conductive via and the first dielectric layer, as taught by Yokoyama, since a dielectric liner 61 (Yokoyama, Fig. 1A, paragraph 0064) electrically isolates the semiconductor layer 10 (Fig. 1A, paragraph 0055) from conductive layers 30 (Fig. 1A, paragraph 0065).
Regarding claim 12, Sanchez in view of Cheng and Yokoyama discloses the device of claim 11, however Sanchez and Cheng do not disclose a material of the dielectric liner and a material of the first dielectric layer are different.
Yokoyama discloses a material of the dielectric liner 61 (Fig. 1A, paragraph 0064, wherein “Hf oxide; Al.sub.2O.sub.3; Ru oxide; Ta oxide; oxide containing Al, Ru, Ta, or Hf and Si; nitride containing Al, Ru, Ta, or Hf and Si; or oxynitride containing Al, Ru, Ta, or Hf and Si”) and a material of the first dielectric layer 63 (Fig. 1A, paragraph 0064, wherein “SiO.sub.2”) are different.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form a material of the dielectric liner and a material of the first dielectric layer are different, as taught by Yokoyama, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 20, Sanchez in view of Cheng and Yokoyama discloses the device of claim 15, however Sanchez and Cheng do not disclose spacers disposed between end portions of the channel region and the first semiconductor layer, wherein the spacers are in physical contact with both the channel region and the first semiconductor layer.
Yokoyama discloses spacers (24, 26, and Z in Fig. 1A) disposed between end portions of the channel region (portion of 10S2 between 25S and 25D in Fig. 1A) and the first semiconductor layer (upper portion of 10S2 in Fig. 1A), wherein the spacers (24, 26, and Z in Fig. 1A) are in physical contact with both the channel region (portion of 10S2 between 25S and 25D in Fig. 1A) and the first semiconductor layer (upper portion of 10S2 in Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form spacers disposed between end portions of the channel region and the first semiconductor layer, wherein the spacers are in physical contact with both the channel region and the first semiconductor layer, as taught by Yokoyama, since the periphery of the contact plug P (Yokoyama, Fig. 1A, paragraph 0089) passing through the semiconductor substrate 10 (Yokoyama, Fig. 1A, paragraph 0089) is covered by the insulating film Z (Yokoyama, Fig. 1A, paragraph 0089) such that the contact plug P (Yokoyama, Fig. 1A, paragraph 0089) is reliably insulated from the semiconductor substrate 10 (Yokoyama, Fig. 1A, paragraph 0089) and an unintentional short circuit between the contact plug P (Yokoyama, Fig. 1A, paragraph 0089) and the semiconductor substrate 10 (Yokoyama, Fig. 1A, paragraph 0089) is avoided.
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez in view of Cheng as applied to claim 7 above, and further in view of Faltermeie et al. (US 2010/0187578) (hereafter Faltermeie).
Regarding claim 13, Sanchez in view of Cheng discloses the device of claim 7, however Sanchez and Cheng do not disclose the semiconductor layer has curved sidewalls.
Faltermeie discloses the semiconductor layer (10 and 20 in Fig. 7, paragraph 0017) has curved sidewalls (see paragraph 0019, wherein “semicircular in shape”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form the semiconductor layer has curved sidewalls, as taught by Faltermeie, since the stressed material 26 (Faltermeie, Fig. 7, paragraph 0021) becomes embedded in the undercut areas 24 (Faltermeie, Fig. 7, paragraph 0021) of the channel region 20 (Faltermeie, Fig. 7, paragraph 0021) under the gate conductor 14 (Faltermeie, Fig. 7, paragraph 0021) where it can cause strain within the channel region 20 (Faltermeie, Fig. 7, paragraph 0021).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sanchez in view of Cheng as applied to claim 7 above, and further in view of Kim et al. (US 2020/0373331) (hereafter Kim).
Regarding claim 17, Sanchez in view of Cheng discloses the device of claim 16, however Sanchez and Cheng do not disclose a first liner layer and a second liner layer disposed between a portion of the backside power rail and the first dielectric layer, wherein a first material of the first liner layer, a second material of the second liner layer, and a third material of the first dielectric layer are different from each other.
Kim discloses a first liner layer 105 (Fig. 1B, paragraph 0042) and a second liner layer 110 (Fig. 1B, paragraph 0042) disposed between a portion of the backside power rail (180, 160, and 150 in Fig. 1B) and the first dielectric layer 112 (Fig. 1B, paragraph 0020), wherein a first material of the first liner layer 105 (Fig. 1B, paragraph 0042, wherein “aluminum oxide (Al.sub.2O.sub.3)”), a second material of the second liner layer 110 (Fig. 1B, paragraph 0042, wherein “SiC”), and a third material (see paragraph 0010, wherein “SiO.sub.2”) of the first dielectric layer 112 (Fig. 1B, paragraph 0020, wherein “silicon oxide layer”) are different from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form a first liner layer and a second liner layer disposed between a portion of the backside power rail and the first dielectric layer, wherein a first material of the first liner layer, a second material of the second liner layer, and a third material of the first dielectric layer are different from each other, as taught by Kim, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 18, Sanchez in view of Cheng and Kim discloses the device of claim 17, however Sanchez and Cheng do not disclose the first material comprises aluminum oxide, the second material comprises silicon carbide, and the third material comprises silicon oxide.
Kim discloses the first material 105 (Fig. 1B, paragraph 0042, wherein “aluminum oxide (Al.sub.2O.sub.3)”) comprises aluminum oxide, the second material 110 (Fig. 1B, paragraph 0042, wherein “SiC”) comprises silicon carbide, and the third material 112 (Fig. 1B, paragraph 0010, wherein “SiO.sub.2”) comprises silicon oxide.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sanchez in view of Cheng to form the first material comprises aluminum oxide, the second material comprises silicon carbide, and the third material comprises silicon oxide, as taught by Kim, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Response to Arguments
1. Applicant's arguments filed 1/2/2026 have been fully considered.
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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