DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings Objections
Drawings 8-9 are objected to for:
Missing a reference number 800 on fig. 8 that is discussed in the disclosure at least on par. 57. Similarly, reference 900 is discussed on par. 59 but missed on fig. 9
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-12, 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun/ETRI et al. USPG Pub 2022/0197764 (herein after ETRI) in view of Wong (Springer), H. Y. Wong, “Quantum Oracles and Construction of Quantum Gate Matrices,” Ch. 22, in Introduction to Quantum Computing, Springer (2022) (hereafter Springer).
Regarding claims 1 and 11, ETRI computer-implemented method and computer system for diagnosing a digital circuit (see ¶[0011-0014] and fig. 1A-B; quantum diagnostic circuit and quantum characteristic diagnostic method), the method comprising:
a processor (ETRI ¶[0031]; CPU 1111); and
a storage device storing instructions that when executed by the processor cause the computer to perform a method for diagnosing a digital circuit (ETRI ¶[0062] …Referring to FIGS. 1A and 6, it is possible to easily diagnose the state and characteristics of physical qubits in the quantum superposition and entanglement state through the application of the quantum diagnostic circuit of the present disclosure. In addition, when a problem is found during quantum simulation or circuit execution, it is possible to collect characteristic information that may remove the problem in advance. …);
obtaining, by a computer, a design of the digital circuit (ETRI ¶[0011] … a quantum diagnostic circuit and a quantum characteristic diagnosis method for facilitating the diagnosis of errors or characteristics in designing and verifying a quantum circuit… see further ¶[0024]–[0029], ¶[0063]–[0069] for teaches of obtaining/decoding and installing a diagnostic circuit and preparing input vectors);
generating [a design of] a diagnostic circuit by augmenting [the design of the digital circuit] based on a number of fault-emulating subcircuits (ETRI ¶[0013], ¶[0035]–[0041], FIG. 2A–2C; ¶[0042]–[0047], FIG. 3; ¶[0048]–[0055], FIGS. 4–5: teaches generating a diagnostic-circuit design by augmentation with fault-emulating subcircuits constructing a dedicated quantum diagnostic circuit to probe qubit/gate characteristics … Diagnostic circuit structure and gates … H + cascaded entangling gates or replacement gates) and varying input vectors/lookup patterns to detect faulty elements);
constructing a quantum diagnostic circuit based on the design of the quantum oracle circuit (ETRI ¶[0013], ¶[0024]–[0029], ¶[0042]–[0056], FIG. 3–4: teaches constructing diagnostic circuits and installing/executing them … ¶[0048]–[0054]: teaches the use of alternative gate implementations for CNOT to suit hardware capabilities); and
observing states of the quantum diagnostic circuit to determine probability distributions of one or more faults in the digital circuit (ETRI ¶[0026]–[0029] discusses teaching of measurement and analysis of output state vectors; use of lookup tables and patterns to diagnose errors in qubits/gates: measurement flow and state collection).
ETSI fails to explicitly teach, however Springer teaches:
generating a design of a diagnostic circuit by augmenting the design of the digital circuit based on a number of fault-emulating subcircuits (Springer Ch. 22, 22.2–22.3 teaches how to encode an arbitrary classical function f(x) as a quantum oracle Uf (XOR and phase oracles) and how to construct the matrix/subcircuits/gate representation for a given oracle … Ch. 22.2-22.23 teaches create an equivalent oracle when we need to test the circuit black box… Example 22.4 showing CNOT as an oracle; measurement on IBM-Q and collection of outcomes. Examiner/interpretation relies on applicant’s Spec pars. 34-35 where “fault-emulating subcircuit” is discussed as a subcircuit added to a classical design that, via assumable inputs or equivalent control signals, reproduces a modeled fault behavior at a gate output by forcing or modifying the logical signal values... “quantum oracle circuit” is the Uf mapping and quantum replacement described at [0053]–[0057]; “observing states … determine probability distributions” is the repeated measurement and statistics collection in [0061], [0069]…. … Ch. 22 teaches generating a design of a diagnostic circuit by representing an arbitrary classical function f(x) as a quantum oracle Uf and constructing an oracle circuit by allocating query and auxiliary qubits and replacing classical logic by quantum subcircuits… create an equivalent oracle when we need to test the circuit black box (see Ch. 22.2 and Example 22.4) … the machinery for implementing any classical function (including a diagnostic/fault function) as a quantum oracle is disclosed… Interpretation is consistent with the applicant’s disclosure ¶¶ [0032]–[0039], [0053]–[0059] where discussed “diagnosing a digital circuit” as an application-level task that can be formulated as a classical Boolean function); and
converting the design of the diagnostic circuit to a design of a quantum oracle circuit (Springer Ch. 22.2.1, Eq. (22.1) n XOR quantum oracle is defined as that it will keep the n MSB unchanged but the m LSB will be changed to y ⊕ f(x). … Uf |x_n|y_m = |x_n | y ⊕ f(x)_m… Ch. 22.2, creating oracle Uf when we need to test circuit as a black box… Ch. 22.2.2, a quantum oracle can be used to express the effect of f(x) to achieve the final goal… see further the CNOT as an oracle, Example 22.4 … the teaching of converting a given classical mapping into a quantum-oracle Uf circuit is discussed… pp. 206–212; general oracle/measurement material… Example 22.4, Fig. 22.3: shows concrete oracle realizations (CNOT example) and remarks about running on real hardware: “When it is run on a real computer, occasionally it measures ‘0’ due to errors.” Fig. 22.3 discussion, p. 212… Wong teaches preparing inputs, executing a quantum oracle Uf, and measuring the oracle’s output states (including discussion of real-device measurement outcomes and errors); repeated measurements yield empirical counts that approximate the oracle’s output probability distribution).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the of the claimed invention was made to modify the teachings of ITRI with the teachings of Springer because quantum computing is a modern and enhanced method of resolving design of circuit fault diagnosis problems and using an oracle formulation is a common, predictable way to express a classical mapping as a unitary for implementation in different quantum circuit styles (Ch. 22.2).
Regarding claims 2 and 12, ITRI and Springer tach the method and computer system computer system of claim 11, ETRI further teaches wherein augmenting the design of the digital circuit comprises coupling a fault-emulating subcircuit to an output of each logic gate in the digital circuit (ETRI ¶[0048]–[0056] discloses diagnostic circuit construction and alternative gate implementations and shows concern for implementation fidelity and gate support).
Regarding claims 4 and 14, ITRI and Springer teach the method and computer system of claim 11, wherein converting the design of the diagnostic circuit to the design of the quantum oracle circuit comprises:
representing each primary input of the diagnostic circuit using one qubit (ETRI FIG.3, FIG.5; input test vector q1, q2, q3 and q4 are each single qubit input to the “Diagnostic Circuit Unit 330” … see further ¶[0042]–[0056]); and
representing each fault input of the diagnostic circuit using one qubit (fig. 3 and ; each q1-q4 represent fault input for the quantum diagnostic circuit 300… see further ¶ [0063]–[0069]).
Regarding claims 5 and 15, ITRI and Springer teach the method and computer system of claim 14, ETRI wherein converting the design of the diagnostic circuit to the design of the quantum oracle circuit comprises replacing a logic gate in the diagnostic circuit with a corresponding quantum subcircuit comprising one or more quantum gates (ETRI FIGS.4A–4C, ¶[0056]–[0059] inserting restoration/uncompute steps and hardware‑aware gate sequences).
Regarding claims 6 and 16, ITRI and Springer teach the method and computer system of claim 15, ITRI further wherein the quantum gates comprise one or more of: a Pauli-X gate, a Hadamard gate, a Controlled NOT (CNOT) gate, and a Controlled Controlled NOT (CCNOT) gate (ETRI ¶[0040] CNOT gate).
Regarding claims 7 and 17, ITRI and Springer teach the method and computer system of claim 11, ITRI further teaches wherein constructing the quantum diagnostic circuit comprises applying a Hadamard gate to a qubit representing a fault input of the diagnostic circuit (ETRI ¶[0044] & Fig. 3 below for CNOT gate …see further ¶[0048]–[0056] for hardware-aware replacement and selection of qubits for operations (choice of replacement gates, hardware constraints ).
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Regarding claims 8 and 18, ITRI and Springer teach the method and computer system of claim 11, ETRI further teaches wherein observing the states of the quantum diagnostic circuit comprises observing the states of the qubit representing the fault input (ETRI ¶[0056, 58] when the final state by the application of the measurement circuit 338 is 4-qubit, like the output unit 340, 2.sup.4=16 quantum probability amplitude state values may be obtained, and it is necessary to check whether it is the Bell state… normal … not normal… See further Fig. 6 for installing, running, measuring a diagnostic circuit and iterating input vectors per a lookup table).
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun/ETRI et al. USPG Pub 2022/0197764 (herein after ETRI) in view of Wong (Springer), H. Y. Wong, “Quantum Oracles and Construction of Quantum Gate Matrices,” Ch. 22, in Introduction to Quantum Computing, Springer (2022) (hereafter Springer) further in view of HAPKE et al. US 20100229061 A1.
Regarding claims 3 and 13, ITRI and Springer teach the method and computer system of claim 12 but fail to explicitly teach wherein the fault-emulating subcircuit is to emulate one of: a stuck-at-one fault; a stuck-at-zero fault; a wrong-component-type fault; a connection-failure fault; and a bridging fault.
However, HAPKE et al. teaches fault-emulating subcircuit to emulate stuck at zero ([0046]… In FIG. 4a, an SA0 (Stuck-At 0) fault is at the cell input D0. The SA-ATPG model would define D0=1, S0=0, and S1=0. ... ; claim 14 the standard-model defects include stuck-at defects and the standard fault models include stuck-at fault models).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the of the claimed invention was made to modify the teachings of ITRI and Springer in view of HAPKE et al. to provide testing of integrated circuits in modeling defects including different plurality types of faults and generating high quality test patterns to test ICs for defects that occur during or after the manufacturing process (see ¶[0002, 0005).
Claim(s) 9-10 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun/ETRI et al. USPG Pub 2022/0197764 (herein after ETRI) in view of Wong (Springer), H. Y. Wong, “Quantum Oracles and Construction of Quantum Gate Matrices,” Ch. 22, in Introduction to Quantum Computing, Springer (2022) (hereafter Springer) further in view of Kiryu US 20070273401 A1.
Regarding claims 9 and 19 ITRI and Springer teach the method and computer system of claim 11, ETRI further teaches wherein the method further comprises coupling multiple outputs of the diagnostic circuit to [a single AND] gate, and wherein observing the states of the quantum diagnostic circuit comprises observing the states of the qubit representing an output of [the AND] gate (ETRI ¶[0013]; ¶[0024]–[0033]; FIG. 3–4; FIG. 5; diagnostic circuit framework: software/hardware apparatus that decodes and installs diagnostic circuits, initializes qubits to known values, executes gate sequences (H plus cascaded entangling or hardware-aware replacements), measures output state vectors, and uses predefined lookup tables/patterns to diagnose faulty elements and gate support).
The combination of ITRI and Springer fails to explicitly teach, however Kiryu teaches use of a single AND gate (Kiryu [0015] In one embodiment, the weighting logic comprises a number of input ports, an output port, and intervening AND gates and MUX. One input is coupled directly to the MUX and each remaining input is couple to an AND gate. The output of each AND gate is coupled to … a single AND gate … AND gate 570; …[0028] … methods associated with integrated circuits (ICs) to manage the composition of input test bit patterns to improve the fault coverage of logic built-in-self-tests (LBISTs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the of the claimed invention was made to modify the teachings of ITRI and Springer in view of Kiryu to incorporate Kiryu’s well-known DFT/test-bench practices (pattern generation, parameter optimization via metrics, sampling/comparison) to improve diagnostic coverage and automate parameter selection. The combination applies standard, predictable techniques from quantum circuit diagnostics (ETRI) and oracle encoding (Wong) together with established DFT optimization and test orchestration (Kiryu), yielding a system and method with a reasonable expectation of success.
Regarding claims 10 and 20, ITRI and Springer teach the method and computer system of claim 19, ETRI further teaches wherein the method further comprises collecting statistics of the observed states of the quantum diagnostic circuit based on the observed states of the qubit representing the fault input and the observed states of the qubit representing an output of the [AND] gate (ITRI (FIG. 5; ¶[0056]–[0071]; [0086]–[0088] predefined lookup patterns correlating input vectors to output state vectors for 4-qubit Bell/GHZ diagnostics; diagnosis workflow iterating inputs and checking whether outputs fall within target ranges). Springer on Ch. 16.5.3 discloses use of AND gate in quantum circuit including CCNOT (…the third qubit value equals a AND b and thus it can act as a classical AND gate, with the first two qubits as the inputs and the third qubit as the output…)
The combination of ITRI and Springer fails to explicitly teach, however Kiryu teaches use of the AND gate (Kiryu ¶[0039-44] and FIGS. 3-4ampling/dumping pre/post patterns, comparing outputs to expected/golden signatures, and using metrics to select/validate parameters — a classical DFT analogue of lookup/golden comparison … [0015] In one embodiment, the weighting logic comprises a number of input ports, an output port, and intervening AND gates and MUX. One input is coupled directly to the MUX and each remaining input is couple to an AND gate. The output of each AND gate is coupled to … a single AND gate … AND gate 570; …[0028] … methods associated with integrated circuits (ICs) to manage the composition of input test bit patterns to improve the fault coverage of logic built-in-self-tests (LBISTs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the of the claimed invention was made to modify the teachings of ITRI and Springer in view of Kiryu to incorporate Kiryu’s well-known DFT/test-bench practices (pattern generation, parameter optimization via metrics, sampling/comparison) to improve diagnostic coverage and automate parameter selection. The combination applies standard, predictable techniques from quantum circuit diagnostics (ETRI) and oracle encoding (Wong) together with established DFT optimization and test orchestration (Kiryu), yielding a system and method with a reasonable expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fujitsu, US 20250348645 A1 teaches converting non-basic gates to equivalent circuits of basic gates; ancilla policies; pipelines to produce runnable circuits: ¶[0042]–[0047], ¶[0086]–[0090], ¶[0169]–[0176], ¶[0221]–[0229], ¶[0231]–[0287] teaches implementability via decomposition into supported basic gates and ancilla management; circuit generation pipeline: ¶[0098]–[0116], ¶[0117]–[0135], ¶[0221]–[0229], ¶[0231]–[0287].
US 20250348645 A1 teaches QUANTUM CIRCUIT DESIGN SUPPORT METHOD AND QUANTUM CIRCUIT DESIGN SUPPORT APPARATUS
US 20230130156 A1 teaches a SYSTEM AND METHOD TO DESIGN PHOTONIC CIRCUITS FOR PREPARING GAUSSIAN AND NON-GAUSSIAN STATES
US 20160125102 A1 teaches a method for generate the RQL circuit design
US 4441075 A teaches an excellent diagnostic resolution of single stuck faults on chip pins or on the package wiring is achievable with the test procedure described above. Based on the simple tests described above, single stuck faults are immediately diagnosable to the failing package net. Fora package net that starts at a single chip output pin or package input pin and terminates at a single chip input pin or package output pin, the diagnostic resolution cannot be enhanced any further. For package nets that terminate at more than one chip input pin or package output pin it is possible to diagnose single stuck faults to the portion of the net which connects to the individual chip input pin or package output pin--since each such portion of the net is independently observable as in FIG. 22. For package nets that start at more than one chip output pin or package input pin it is possible to diagnose distinguishable single stuck faults to the portion of the net that is unique to an individual chip output pin or to a package input pin since the effect of each portion can be observed independently in different tests as in FIG. 23
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/ELENI A SHIFERAW/Supervisory Patent Examiner, Art Unit 2497