DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 28, 2023, March 1, 2024, May 9, 2024, November 24, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Three-Dimensional Memory Device With Through-Stack Contact Via with Conductive Fins.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on November 24, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines: 12-16 recites the limitation “wherein the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.” It is unclear if the conductive pillar portion or the conductive fin portion is meant to the have the “a first annular bottom surface segment”. For purposes of examination this will be interpreted as “wherein the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and the conductive fin portion having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5-6 of copending Application No. 18/532,221 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the copending application recite each limitation of the instant claims as detailed below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
18/532,221
1. A memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers, wherein the first alternating stack comprises first stepped surfaces in a contact region; a first dielectric material portion overlying the first stepped surfaces of the first alternating stack; a memory opening vertically extending at least through each layer within the first alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; and a first contact via structure vertically extending at least from a bottommost surface of the first alternating stack, through the first dielectric material portion, and to a horizontal plane located at or above a top surface of the memory opening fill structure, wherein the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
1. A memory device, comprising: an alternating stack of insulating layers and electrically conductive layers, the alternating stack comprising stepped surfaces; a memory opening vertically extending through each layer within the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; a dielectric material layer that extends from a bottommost vertical step of the stepped surfaces to a topmost vertical step of the stepped surfaces; and a contact via structure comprising: an upper contact via portion having an annular bottom surface that contacts an annular top surface of a first electrically conductive layer of the electrically conductive layers; and a lower contact via portion that vertically extends through a first subset of the electrically conductive layers that underlie the first electrically conductive layer, wherein the lower contact via portion is narrower than the upper contact via portion.
5. The memory device of claim 1, further comprising a stepped dielectric material portion overlying the dielectric material layer, wherein the upper contact via portion vertically extends through the stepped dielectric material portion.6. The memory device of claim 5, further comprising a lower insulating spacer that comprises a tubular insulating portion and annular insulating plates, wherein: the tubular insulating portion vertically extends through each electrically conductive layer within the first subset of the electrically conductive layers and comprises a lower inner cylindrical sidewall that contacts a cylindrical sidewall of the lower contact via portion; and the annular insulating plates are adjoined to outer cylindrical surface segments of the tubular insulating portion and laterally protrude outward from the tubular insulating portion at levels of a first subset of the insulating layers that underlie the first electrically conductive layer.
Claims 1-3 and 6-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 5-12 of copending Application No. 18/455,988 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the copending application recite each limitation of the instant claims as detailed below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
18/455,988
1. A memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers, wherein the first alternating stack comprises first stepped surfaces in a contact region; a first dielectric material portion overlying the first stepped surfaces of the first alternating stack; a memory opening vertically extending at least through each layer within the first alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; and a first contact via structure vertically extending at least from a bottommost surface of the first alternating stack, through the first dielectric material portion, and to a horizontal plane located at or above a top surface of the memory opening fill structure, wherein the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
1. A memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a memory opening vertically extending at least through each layer within the alternating stack; a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; and a bundled contact via structure vertically extending through a plurality of bottommost electrically conductive layers of the electrically conductive layers, and laterally contacting each of the plurality of the bottommost electrically conductive layers.
3. The memory device of claim 1, wherein: an alternating stack comprises stepped surfaces in a contact region; a first stepped dielectric material portion overlies the stepped surfaces of the alternating stack; and the bundled contact via structure vertically extends through the first stepped dielectric material portion.5. The memory device of claim 3, further comprising a contact-level dielectric layer overlying the alternating stack and the first stepped dielectric material portion, wherein a top surface of the bundled contact via structure is coplanar with a top surface of the contact-level dielectric layer.
6. The memory device of claim 3, wherein: the bundled contact via structure contacts a respective cylindrical sidewall of each of the plurality of the bottommost electrically conductive layers; and the cylindrical sidewalls of the plurality of the bottommost electrically conductive layers are vertically coincident with each other.7. The memory device of claim 6, further comprising a first contact via structure vertically extending at least from a bottommost surface of the alternating stack, through the first stepped dielectric material portion, and to a horizontal plane located at or above a top surface of the memory opening fill structure, and contacting an annular top surface segment of one of the electrically conductive layers that overlies the plurality of the bottommost electrically conductive layers.
8. The memory device of claim 7, wherein: the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion; and the conductive fin portion has a first annular bottom surface segment contacting the annular top surface segment of the one of the electrically conductive layers.
2. The memory device of claim 1, further comprising a vertical stack of annular insulating plates laterally surrounding and contacting the conductive pillar portion and underlying the conductive fin portion.
9. The memory device of claim 8, further comprising a vertical stack of annular insulating plates laterally surrounding and contacting the conductive pillar portion and underlying the conductive fin portion.
3. The memory device of claim 2, wherein a topmost annular insulating plate within the vertical stack of annular insulating plates is in contact with a second annular bottom surface segment of the conductive fin portion.
10. The memory device of claim 8, wherein a topmost annular insulating plate within the vertical stack of annular insulating plates is in contact with a second annular bottom surface segment of the conductive fin portion.
6. The memory device of claim 2, wherein each annular insulating plate within the vertical stack of annular insulating plates has a lateral width which laterally offsets a respective one of the electrically conductive layers located at a same vertical level from the conductive pillar portion by a uniform lateral offset distance.
11. The memory device of claim 8, wherein each annular insulating plate within the vertical stack of annular insulating plates has a lateral width which laterally offsets a respective one of the electrically conductive layers located at a same vertical level from the conductive pillar portion by a uniform lateral offset distance.
7. The memory device of claim 1, wherein the conductive fin portion comprises an annular top surface in contact with an annular planar surface segment of the first dielectric material portion.
12. The memory device of claim 8, wherein the conductive fin portion comprises an annular top surface in contact with an annular planar surface segment of the first stepped dielectric material portion.
Allowable Subject Matter
Claims 1-14 would be allowed if rewritten to overcome the 112 rejection above and a terminal disclaimer was filed to overcome the pending provisional double patenting above. The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Tsutsumi (US 2024/0215243), Dunga (US 2024/0373633), Kubo (US 2025/0014990), Pachamuthu (US 2015/0236038), Zhou (US 2019/0229125), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-14 depend), the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pachamuthu (US 2015/0236038) discloses (Fig. 22) with a backside contact via structure 76 with a laterally protruding portion but it does not disclose an annular bottom surface of the via structure contacting annular top surface of gate electrodes.
Zhou (US 2019/0229125) discloses (Fig. 33) a conductive contact layer 67L which has a laterally protruding portion, but it does not disclose the portion having an annular bottom surface contacting top annular surface of the electrically conductive layers.
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/G.G.R/Examiner, Art Unit 2812