DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-19 and 21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 December 2025.
Information Disclosure Statement
The information disclosure statement filed 28 July 2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. A copy of Non-Patent Literature Document #1: Johnson, “PCB Design Guidelines for QFN and DQFN Packages”, Microchip Technology Inc. Application Note, 2014-2021 has not been provided.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims use the limitations “leads around a perimeter”, “a plurality of the leads”, “the leads”, “the leads under the relief recess”, “a majority of the leads”, “the leads are exposed”, “top surfaces of the leads”, “the exposed side faces of the leads”, “the leads extend”, “a thickness of the leads under the relief recess”, etc. that do not make it clear which leads of the “leads around a perimeter of the semiconductor package” are required to meet the specification of the later limitations, whether it is all the leads, leads under the relief recess, a majority of the leads, exposed at the relief recess, extend below a bottom surface of the mold compound, etc.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imori et al. (U.S. 2018/0247883).
Regarding Claim 1, Imori et al., Figures 4a-b and 6, discloses a semiconductor package, comprising:
leads around a perimeter of the semiconductor package (leads 20);
a microelectronic component electrically coupled to a plurality of the leads (microelectronic component 30);
a mold compound contacting the leads and the microelectronic component, wherein: the mold compound is electrically insulating (mold compound 40);
the mold compound is recessed around the perimeter to provide a relief recess having a relief width greater than a thickness of the leads under the relief recess (recess T);
a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess (leads 20, recess T); and
exposed side faces of a majority of the leads are characteristic of sawn surfaces ([0044]).
Regarding Claim 2, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein a top half of a side face of the relief recess along the mold compound is vertical with respect to a top surface of the mold compound (mold compound 40).
Regarding Claim 3, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein the leads are exposed at the relief recess (leads 20, mold compound 40, package 300).
Regarding Claim 4, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein top surfaces of the leads are exposed under the relief recess (leads 20, mold compound 40, package 300).
Regarding Claim 5, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein top surfaces of the leads are covered by the mold compound under the relief recess (leads 20, mold compound 40).
Regarding Claim 6, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein the exposed side faces of the majority of the leads being characteristic of sawn surfaces includes the exposed side faces of the majority of the leads being free of vertical striations ([0044]).
Regarding Claim 7, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein the exposed side faces of the majority of the leads being characteristic of sawn surfaces includes the exposed side faces of the majority of the leads having burrs along bottom edges ([0044]).
Regarding Claim 8, Imori et al., Figures 4a-b and 6, further discloses the semiconductor package of claim 1, wherein the leads extend below a bottom surface of the mold compound (leads 20, mold compound 40).
Regarding Claim 20, Imori et al., Figures 4a-b and 6, discloses a semiconductor package, comprising:
leads around a perimeter of the semiconductor package (leads 20);
a microelectronic component electrically coupled to a plurality of the leads (microelectronic component 30); and
a mold compound contacting the leads and the microelectronic component, wherein (mold compound 40):
the mold compound is electrically insulating;
the mold compound is recessed around the perimeter to provide a relief recess (recess T);
the relief recess has a relief width greater than a thickness of the leads under the relief recess (leads 20, recess T);
a top half of a side face of the relief recess along the mold compound is vertical with respect to a top surface of the mold compound (recess T);
an internal corner of the relief recess has a rounded profile (package 300);
a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess (leads 20, recess T); and
exposed side faces of a majority of the leads are characteristic of sawn surfaces ([0044]).
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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