Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-12, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Chang, et al. (US 20150236150 A1).
Regarding claim 1, FIG. 1 of Chen, Chang, et al. teaches an apparatus comprising:
a substrate (100; FIG. 1; paragraph 0039) comprising a first well having a first doping (102; FIG. 1; paragraph 0039) and a second well region having a second doping (104; FIG. 1; paragraph 0039);
a source (108; FIG. 1; paragraph 0039) formed in the first well (102; FIG. 1; paragraph 0039); and
a gate (106, 112; FIG. 1; paragraph 0039) (Chen, Chang, et al. features two gates) comprising an undoped block (107; FIG. 1; paragraph 0041) and a doped block (113; FIG. 1; paragraph 0043), the undoped block (106, 107; FIG. 1; paragraph 0041) disposed at least partially on the source (108; FIG. 1; paragraph 0039) (FIG.1 of Chen, Chang, et al. shows the corner of the undoped gate and the source touching), first well (102; FIG. 1; paragraph 0041), and second well (104; FIG. 1; paragraph 0041), wherein the doped block (112, 113; FIG. 1; paragraph 0043) is disposed at least partially on the second well (104; FIG. 1; paragraph 0043).
Regarding claim 2, FIG. 1 of Chen, Chang, et al. teaches the apparatus of claim 1, wherein the gate is a split gate (106, 112; FIG. 1; paragraph 0048), wherein the doped block (106, 107; FIG. 1; paragraph 0041) and undoped block (112, 113; FIG. 1; paragraph 0043) are separated (130; FIG. 1; paragraph 0048).
Regarding claim 3, Chen, Chang et al. teach the apparatus of claim 1, wherein the gate is formed of polycrystalline silicon (paragraph 0018).
Regarding claim 4, Chen, Chang, et al. teach the apparatus of claim 1, wherein the first doping is a p-type doping (paragraph 0040), and the second doping is an n-type doping (paragraph 0040).
Regarding claim 5, Chen, Chang, et al. teach the apparatus of claim 1, wherein the source (108; FIG. 1; paragraph 0042) is a heavily n-type doped region in the first well (108; FIG. 1; paragraph 0042).
Regarding claim 10, FIG. 1 of Chen, Chang, et al. teaches a semiconductor device (paragraph 0006) comprising:
a source (108; FIG. 1; paragraph 0039);
a drain (110; FIG. 1; paragraph 0039); and
a gate (106; FIG. 1; paragraph 0041) disposed on a substrate (100; FIG. 1; paragraph 0041), the gate (106, 112; FIG. 1; paragraph 0039) comprising an undoped region (106, 107; FIG. 1; paragraph 0041) and a doped region (112, 113; FIG. 1; paragraph 0043), the undoped region (106, 107; FIG. 1; paragraph 0041) disposed at least partially on the source (108; FIG. 1; paragraph 0042) wherein the doped region (112, 113; FIG. 1; paragraph 0043) is disposed between the drain (110; FIG. 1; paragraph 0043) and source (108; FIG. 1; paragraph 0043).
Regarding claim 11, FIG. 1 of Chen, Chang, et al. teach the apparatus of claim 10, wherein the gate is a split gate (106, 112; FIG. 1; paragraph 0048), wherein the doped region (106, 107; FIG. 1; paragraph 0041) and undoped regions (112, 113; FIG. 1; paragraph 0043) are separate respective blocks (130; FIG. 1; paragraph 0048) of dielectric material (105, 111; FIG.1; paragraph 0043).
Regrading claim 12, Chen, Chang, et al. teach the apparatus of claim 10, wherein the gate is formed of polycrystalline silicon (paragraph 0018).
Regarding claim 16, FIG. 1 of Chen, Chang, et al. teaches an apparatus comprising:
a substrate (100; FIG.1; paragraph 0039) comprising a first well having a first doping (102; FIG.1; paragraph 0039) and a second well region having a second doping (104; FIG.1; paragraph 0039); and
a gate (106, 112; FIG. 1; paragraph 0039) (Chen, Chang, et al. features two gates) comprising an undoped block (107; FIG. 1; paragraph 0041) and a doped block (113; FIG. 1; paragraph 0043), the undoped block (106, 107; FIG. 1; paragraph 0041) disposed at least partially on the source (108; FIG. 1; paragraph 0039) (FIG.1 of Chen, Chang, et al. shows the corner of the undoped gate and the source touching), first well (102; FIG. 1; paragraph 0041), and second well (104; FIG. 1; paragraph 0041), wherein the doped block (112, 113; FIG. 1; paragraph 0043) is disposed at least partially on the second well (104; FIG. 1; paragraph 0043).
Regarding claim 17, FIG. 1 of Chen, Chang, et al. teach the substrate of claim 16, wherein the gate is a split gate (106, 112; FIG. 1; paragraph 0048), wherein the doped block (106, 107; FIG. 1; paragraph 0041) and undoped block (112, 113; FIG. 1; paragraph 0043) are separate respective blocks (130; FIG. 1; paragraph 0048) of dielectric material (105, 111; FIG.1; paragraph 0043).
Regarding claim 18, Chen, Chang, et al. teach the substrate of claim 16, wherein the gate is formed of polycrystalline silicon (paragraph 0018).
Regarding claim 19, Chen, Chang, et al. teach the substrate of claim 16, wherein the first doping is a p-type doping (paragraph 0040), and the second doping is an n-type doping (paragraph 0040).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 13-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chang, et al. in view of Hu (US 20170186783 A1).
Regarding claim 6, Chen, Chang, et al teach the apparatus of claim 1. Chen, Chang, et al. do not teach the doped block having at least one of a light doping implant or heavy doping implant applied.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
Chen, Chang, et al. and Hu are both analogous to the claimed invention in that they involve constructing semiconductor devices with doped gates. Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Chen, Chang, et al. to incorporate the teachings of Hu and give the doped portion of the gate a light doping implant and/or heavy doping implant. Doing so would so would set up a structure that allow the reduction of leakage current (paragraph 0007).
Regarding claim 7, the combination of Chen, Chang, et al. in view of Hu teaches the apparatus of claim 6. Chen, Chang et al. does not teach the doped block having an n-type lightly doped drain implant and n-type heavy doping implant applied.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to make use of both an n-type LDD implant and an n-type heavy doping implant in the doped block. Doing so would so would set up a structure that allow the reduction of leakage current (paragraph 0007).
Regarding claim 8, the combination of Chen, Chang, et al. in view of Hu teaches the apparatus of claim 6. Chen, Chang, et al. further teaches the second doping (104; FIG. 1; paragraph 0040) as an n-type doping (paragraph 0040). Cehn, Chang, et al. does not teach the implant includes a light and heavy doping of a same type as the second doping.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to make both the gate doping and the second well region doping n-type. The consistency in doping type is necessary to reduce leakage current (paragraph 0007).
Regarding claim 13, Chen, Chang, et al. teach the apparatus of claim 10. Chen, Chang, et al. do not teach the doped block having at least one of a light doping implant or heavy doping implant applied.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
Chen, Chang, et al. are both analogous to the claimed invention in that they involve constructing semiconductor devices with doped gates. Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Chen, Chang, et al. to incorporate the teachings of Hu and give the doped portion of the gate a light doping implant and/or heavy doping implant. Doing so would so would set up a structure that allow the reduction of leakage current (paragraph 0007).
Regarding claim 14, the combination of Chen, Chang, et al. in view of Hu teaches the apparatus of claim 13. Chen, Chang et al. does not teach the doped block having an n-type lightly doped drain implant and n-type heavy doping implant applied.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to make use of both an n-type LDD implant and an n-type heavy doping implant in the doped block. Doing so would so would set up a structure that allow the reduction of leakage current (paragraph 0007).
Regarding claim 20, Chen, Chang, et al. teach the apparatus of claim 19. Chen, Chang, et al. do not teach the doped block having at least one of a of an n-type lightly doped drain implant and an n-type heavy doping implant applied.
Hu teaches a process for manufacturing an N-type TFT having an LDD structure by using a half-tone mask to subject, in sequence, a gate electrode to two times of etching in such a way that the gate electrode that has been subjected to the first etching operation is used as a shielding layer for N-type heavy doping and the gate electrode that has been subjected to the second etching operation is used as a shielding layer for N-type light doping in order to form the LDD (paragraph 0018).
Chen, Chang, et al. are both analogous to the claimed invention in that they involve constructing semiconductor devices with doped gates. Therefore, it would have been obvious to a person with ordinary skill in the art to have modified Chen, Chang, et al. to incorporate the teachings of Hu and give the doped portion of the gate an n-type lightly doped implant and/or an n-type heavy doping implant. Doing so would be making use of known methods of doping the block and potentially reduce leakage current, keeping the doped block working reliably (paragraph 0007).
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chang, et al. in view of Chen, Kuan, et al. (US 20060113627 A1).
Regarding claim 9, FIG. 1 and FIG. 3 of Chen, Chang, et al. teach the apparatus of claim 1, wherein the substrate includes a shallow trench isolation region (120; FIG. 1; paragraph 0050) formed in the second well (104; FIG. 1; paragraph 0050) (in this case, the STI region is partially in the second well), wherein the shallow trench isolation region (140; FIG. 3; paragraph 0051) is disposed between a drain formed in the second well (104; FIG. 3; paragraph 0051) and the source (106; FIG. 3; paragraph 0050) (in Chen, Chang., et al. this is a separate STI region).
Chen, Chang, et al. do not teach the doped block being disposed at least partially on the shallow trench isolation region.
FIG. 1 of Chen, Kuan, et al. teaches an additional STI structure (18; FIG. 1; paragraph 0023) being formed in a portion of the active area of the semiconductor substrate (10; FIG. 1; paragraph 0023) located under a gate electrode layer (22; FIG. 1; paragraph 0024) that may be formed of doped polysilicon (paragraph 0024).
Chen, Chang, et al. and Chen, Kuan, et al. are analogous to the claimed invention in that they involve semiconductor devices with shallow trench isolation and doped gates. Therefore, it would have been obvious to a person with ordinary skill in the art before the known filing date to have the doped block disposed at least partially on the shallow trench isolation region. Doing so would configure the structure in such a way to help prevent leakage when driving a high voltage (paragraph 0019).
Regarding claim 15, FIG. 1 of Chen, Chang, et al. teaches the apparatus of claim 10, wherein the substrate includes a shallow trench isolation (140; FIG. 3; paragraph 0051) is disposed between a drain formed in the second well (104; FIG. 3; paragraph 0051) and the source (106; FIG. 3; paragraph 0050). Chen, Chang, et al. do not teach the doped block being disposed at least partially on the shallow trench isolation region.
FIG. 1 of Chen, Kuan, et al. teaches an additional STI structure (18; FIG. 1; paragraph 0023) being formed in a portion of the active area of the semiconductor substrate (10; FIG. 1; paragraph 0023) located under a gate electrode layer (22; FIG. 1; paragraph 0024) that may be formed of doped polysilicon (paragraph 0024).
Chen, Chang, et al. and Chen, Kuan, et al. are analogous to the claimed invention in that they involve semiconductor devices with shallow trench isolation and doped gates. Therefore, it would have been obvious to a person with ordinary skill in the art before the known filing date to have the doped block disposed at least partially on the shallow trench isolation region. Doing so would configure the structure in such a way to help prevent leakage when driving a high voltage (paragraph 0019).
Response to Arguments
Applicant’s arguments, see pages 8 and 9 starting with the header "Objections to the Drawings" and ending at the next header, filed February 25th ,2026, with respect to the objections to the drawings have been fully considered and are persuasive. The objection of November 25th, 2025 has been withdrawn.
Applicant’s arguments, see pages 9-11 starting with the header "Rejections Under 35 U.S.C. 112" and ending at the next header, filed February 25, 2026, with respect to the 35 U.S.C. 112(a) rejection of claim 8 have been fully considered and are persuasive. The 35 U.S.C. 112(a) rejection of November 25th, 2025 has been withdrawn.
Applicant's other arguments filed February 25th, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument for claims 1, 2, 10, and 16 that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the gate of claim 1 has to be a single functional structure despite explicitly being made out of two blocks and being a split gate) are not recited in the rejected claim. The argument the first full paragraph of page 11 (under the header) states that “Chen does not teach or suggest a single gate comprising a doped block and an undoped block” when a “single” gate is not specified within the claim, with this aspect being repeated throughout the argument. Another aspect of the argument is the function of the dummy gate, with the argument on the second full paragraph of page 12 (or second from the bottom of page 12) being that “Chen does not even teach that the second gate is a functional gate”, when the function of the gate is never specified within the claims. An argument for claim 2, on the first paragraph of page 13, states the intended function and interpretation of “split gate”, neither of which are elaborated on in the claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Toh, Liu, et al. (US 20170084736 A1) concerns a high voltage device and methods of forming one, with a substrate, source/drain regions, wells, and gates. Toh, Lee, et al. (20120228695 A1) concerns an LDMOS with a first well with a source, a second well with a drain, a substate, and gates. Smayling et al. (US 5275961 A) concerns an insulated- gate field-effect transistor that includes a control gate with a doped region adjacent to the source region and an undoped portion, as well as a drain region.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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/JACOB ALEXANDER VLCEK/Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights