CTNF 18/361,880 CTNF 75758 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Claims 08-25 AIA Applicant's election with traverse of Group II in the reply filed on April 20, 206 is acknowledged. The traversal is on the ground(s) that [ T ] he claim includes seven clauses that recite generic formation of structural features of a device, but does not recite any specific techniques for effecting such formation . As such, the claim is not limited to any particular techniques . This is not found persuasive because, contrary to the Applicant assertion, the limitations of claim 11 clearly claimed very specific method steps , hence techniques, to form the “field relief trench” such as: forming a LOCOS layer in the drain drift region; forming a field relief trench in the drain drift region, the field relief trench being formed by removing the LOCOS layer and having a recessed local oxidation of silicon profile . The requirement is still deemed proper and is therefore made FINAL. Claims 1-19 are pending. Non-Elected invention, Claims 1-10 have been withdrawn from consideration. Action on merits of the Elected Invention, claims 11-19 follows. Information Disclosure Statement The information disclosure statement (IDS) submitted on August 05, 2024 has been considered by the examiner. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: METHOD OF FORMING A FIELD RELIEF DIELECTRIC STRUCTURE IN A DRAIN DRIFT REGION OF AN LDMOS MICROELECTRONIC DEVICE INCLUDING FORMING A LOCOS LAYER AND SUBSEQUENTLY REMOVING THE OXIDE LAYER THEN DEPOSITING HIGH-K DIELECTRIC MATERIAL IN THE REMOVED REGION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites: the method of claim 11, wherein the dielectric liner is formed using an ISSG process . What is an ISSG process ? Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 11-12, 15-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over YU et al. (CN. Pat. No. 115274857) in view of PARK (US. Pub. No. 2013/0187226) . With respect to claim 11, YU teaches a method of forming a microelectronic device, substantially as claimed including: forming a body region (3) and a drain drift region (4) in a semiconductor material (2) of a substrate, the body region (3) having a first conductivity type (P) and the drain drift region (4) having a second conductivity type (N); forming a LOCOS layer (18) in the drain drift region (4); forming a field relief trench in the drain drift region (4), the field relief trench being formed by removing the LOCOS layer (18) and having a recessed local oxidation of silicon profile; forming a high-k field relief dielectric structure (5) over the drain drift region (4) in the field relief trench, the high-k field relief dielectric structure (5) consisting of a high-k field relief dielectric material (SiN), the high-k field relief dielectric structure (5) being greater in thickness than a gate dielectric layer (not shown); forming a gate dielectric layer (not shown) on the substrate, the gate dielectric layer extending part way over the body region (3) and part way over the drain drift region (4), wherein the gate dielectric layer extends over an intersection between the body region (3) and the drain drift region (4); forming a gate electrode (16) over the gate dielectric layer (not shown); forming a source region (7) having a conductivity type contacting the body region (3), the source region (7) having an average dopant density greater than the average dopant density of the body region (3); and forming a drain region (9) having a conductivity type contacting the drain drift region (4), the drain region (9) having an average dopant density greater than an average dopant density of the drain drift region. (See FIGs. 1, 3A-G). Thus, YU is shown to teach all the features of the claim with the exception of explicitly disclosing the conductivity type of the source region and drain region. However, PARK teaches a method of forming a microelectronic device including: forming a body region (220) and a drain drift region (230) in a semiconductor material (210) of a substrate, the body region (220) having a first conductivity type (P) and the drain drift region (230) having a second conductivity type (N); forming a source region (242) having the second conductivity type (N) contacting the body region (220), the source region (242) having an average dopant density greater than the average dopant density of the body region (220); and forming a drain region (248) having the second conductivity type (N) contacting the drain drift region (230), the drain region (248) having an average dopant density greater than an average dopant density of the drain drift region. (See FIG. 2). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the source and drain region of the microelectronic device of YU having the second conductivity type as taught by PARK to form an N-type device. With respect to claim 12, a dielectric liner (not shown) of YU is formed on the drain drift region in the field relief trench, the dielectric liner being between the drain drift region (4) and the high-k field relief dielectric structure (5). (step S4). With respect to claim 15, a field oxide (12) of YU is formed which surrounds the source region (7), the body region (3), the drain drift region (4), and the drain region (9). With respect to claim 16, the field oxide (12) of YU is formed using STI. With respect to claim 18, a high-k field relief dielectric layer (5) of YU is selected from a group consisting of silicon nitride, silicon oxynitride, aluminum oxide, hafnium dioxide, hafnium silicate, zirconium silicate, and zirconium dioxide. With respect to claim 19, the high-k field relief dielectric structure (5) of YU has a dielectric constant of greater than 5 . 07-22-aia AIA Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over YU ‘857 and PARK ‘226 as applied to claim 12 above, and further in view of CHENG et al. (US. Patent No. 6,541,382) . YU, in view of PARK, teaches the method as described in claim 12 above including: the dielectric liner (not shown) is formed on the drain drift region in the field relief trench, the dielectric liner being between the drain drift region and the high-k field relief dielectric structure. Thus, YU and PARK are shown to teach all the features of the claim with the exception of explicitly disclosing the dielectric liner being formed using an ISSG process. However, CHENG teaches a method including: forming a dielectric liner (240) in a shallow trench, wherein the dielectric liner being formed using an ISSG process. (See FIG. 1E). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the liner of YU utilizing ISSG process as taught by CHENG to provide for better corner rounding . 07-22-aia AIA Claim s 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over YU ‘857 and PARK ‘226 as applied to claim s 11 and 15 above, and further in view of LIN et al. (US. Pub. No. 2022/0367611) . YU, in view of PARK, teaches the method as described in claim 11 above including: forming the high-k field relief dielectric structure over the drain drift region in the field relief trench, the high-k field relief dielectric structure consisting of a high-k field relief dielectric material (SiN). Thus, YU, in view of PARK, is shown to teach all the features of the claim with the exception of explicitly disclosing forming a field relief dielectric cap layer on the high-k field relief dielectric structure. However, LIN teaches a method including: forming a high-k field relief dielectric structure (22) over a drain drift region (211) in a field relief trench, the high-k field relief dielectric structure (22) consisting of a high-k field relief dielectric material (SiN), wherein a field relief dielectric cap layer (26) on the high-k field relief dielectric structure (22). (See FIG. 16). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the microelectronic device of YU, in view of PARK, including forming the field relief dielectric cap layer on the high-k field relief dielectric structure as taught by LIN to protect the field relief structure during a subsequent process. With respect to claim 17, in view of LIN, a field relief dielectric cap layer (26) is removed after the field oxide (22’) is formed. (See FIGs. 16-17). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov) . The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/ Primary Examiner, Art Unit 2893 Application/Control Number: 18/361,880 Page 2 Art Unit: 2893 Application/Control Number: 18/361,880 Page 3 Art Unit: 2893 Application/Control Number: 18/361,880 Page 4 Art Unit: 2893 Application/Control Number: 18/361,880 Page 5 Art Unit: 2893 Application/Control Number: 18/361,880 Page 6 Art Unit: 2893 Application/Control Number: 18/361,880 Page 7 Art Unit: 2893 Application/Control Number: 18/361,880 Page 8 Art Unit: 2893 Application/Control Number: 18/361,880 Page 9 Art Unit: 2893
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