Prosecution Insights
Last updated: August 18, 2026
Application No. 18/361,892

ELECTRO-STATIC DISCHARGE PROTECTION DEVICE

Final Rejection §103
Filed
Jul 30, 2023
Priority
Sep 27, 2022 — RE 10-2022-0122746
Examiner
MCDONALD, JASON ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
4 granted / 6 resolved
-1.3% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
47 currently pending
Career history
62
Total Applications
across all art units

Statute-Specific Performance

§103
60.3%
+20.3% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 6 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Status The applicant has amended claims 1-2, 4, 8-9, 12, 16-17, and 19 in the reply dated 26 June 2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (KR 102147138 B1, hereinafter “Yang”), in view of Ma et al (CN 102244076 A, hereinafter “Ma”). Regarding Claim 1 – Yang discloses an electro-static discharge (ESD) protection device ([0001]), comprising: a substrate ([0008]) that includes a first well that has a first conductivity type (220 [0068]) and a second well that has a second conductivity type (230 [0068]); a first diffusion region that has the first conductivity type (243 [0069] and Fig. 7) and a second diffusion region that has the second conductivity type (242 [0069] and Fig. 7), wherein the first diffusion region and the second diffusion region are formed on the first well and connected to a first electrode (Anode [0069] and Fig. 7); a third diffusion region that has the first conductivity type (232 [0069] and Fig. 7) and a fourth diffusion region that has the second conductivity type (231 [0069] and Fig. 7), wherein the third diffusion region and the fourth diffusion region are formed on the second well and connected to a second electrode (Cathode [0069] and Fig. 7); a fifth diffusion region that has the first conductivity type (241 [0069] and Fig. 7) and that is formed on the first well and is adjacent to the second diffusion region (Fig. 7); a sixth diffusion region that has the second conductivity type and that is formed on the second well (234 [0069] and Fig. 7) and is adjacent to the third diffusion region (Fig. 7); a seventh diffusion region that has the second conductivity type and that is formed on the first well (250 [0068] and Fig. 7) and is adjacent to the first diffusion region (Fig. 7); and an eighth diffusion region that has the first conductivity type (251 [0069] and Fig. 7), wherein the seventh diffusion region and the eighth diffusion region are electrically connected to each other (forming a P-N junction as shown in Fig. 7). Yang fails to disclose the eighth diffusion region is formed on the second well and is adjacent to the sixth diffusion region. However, Ma discloses the eighth diffusion region (interpreted as diffusion 38, Ma [0025] and Fig. 3) formed on a well and is electrically connected to the sixth diffusion region (interpreted as diffusion 44, Ma [0025] and Fig. 3). Ma’s diffusion 38 serves the same purpose as the eighth diffusion in the claimed invention, forming part of a P-N diode between the bases of the PNP and NPN structures of the device. Ma discloses an ESD protection device analogous to Yang. Ma teaches adding diodes in series between bipolar (PNP and NPN) bases for the benefit of adjusting the trigger voltage (Ma [0030]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Yang and Ma to add diodes in series between bipolar bases for the benefit of adjusting the trigger voltage. Furthermore, the diode connections between NPN and PNP bases can be formed by any reasonable combination of series P-N junctions to adjust the trigger voltage. Such substitution of known equivalents with inherently similar properties presents a prima facie case of obviousness. See MPEP 2144.06(II). PNG media_image1.png 285 460 media_image1.png Greyscale PNG media_image2.png 285 506 media_image2.png Greyscale Regarding Claim 2 – Yang modified by Ma discloses all the limitations of claim 1. The combination of Yang and Ma further discloses the first conductivity type is an N conductivity type ([0008]), and the second conductivity type is a P conductivity type ([0008]). Regarding Claim 5 – Yang modified by Ma discloses all the limitations of claim 1. The combination of Yang and Ma further discloses the first diffusion region is adjacent to the seventh diffusion region (243 adjacent to 250, Yang Fig. 7), the second diffusion region is adjacent to the first diffusion region (242 adjacent to 243, Yang Fig. 7), and the fifth diffusion region is adjacent to the second diffusion region (241 adjacent to 242, Yang Fig. 7); wherein the sixth diffusion region is adjacent to the eighth diffusion region (electrically, by way of interconnect, 234 adjacent to 251, Yang Fig. 7), the third diffusion region is adjacent to the sixth diffusion region (232 adjacent to 234, Yang Fig. 7), and the fourth diffusion region is adjacent to the third diffusion region (231 adjacent to 232, Fig. 7); and wherein the fifth diffusion region and the eighth diffusion region are formed adjacent to a boundary between the first well and the second well (241 adjacent to boundary, and 233 adjacent to boundary, and directly connected to 251, Yang Fig. 7). Regarding Claim 11 – Yang further discloses the ESD protection device of claim 1, wherein the first electrode is an anode electrode (Anode [0069] and Fig. 7), and the second electrode is a cathode electrode (Cathode [0069] and Fig. 7). Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (KR 102147138 B1, hereinafter “Yang”), in view of Ma et al (CN 102244076 A, hereinafter “Ma”), and further in view of Salcedo et al (US 20060151836 A1, hereinafter “Salcedo”). Regarding Claim 3 – Yang modified by Ma discloses all the limitations of claim 1. The combination of Yang and Ma fails to disclose at least one metal interconnection and at least one via that electrically connect the seventh diffusion region and the eighth diffusion region. However, Salcedo discloses at least one metal interconnection and at least one via that electrically connect diffusion regions (Salcedo [0097] and Fig. 14). Salcedo discloses a similar ESD protection device to Yang. Salcedo teaches using metal interconnections with vias to connect diffusion regions for the benefit of ensuring incoming current is very well distributed along the multi-finger structure (Salcedo [0097]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Yang and Salcedo to use metal interconnections with vias to connect diffusion regions for the benefit of ensuring incoming current is very well distributed along the multi-finger structure. PNG media_image3.png 338 566 media_image3.png Greyscale Regarding Claim 4 – Yang modified by Ma discloses all the limitations of claim 1. The combination of Yang and Ma fails to disclose the substrate includes an epitaxial layer that has the first conductivity type. However, Salcedo discloses the substrate includes an epitaxial layer that has the first conductivity type (Salcedo [0018] and Fig. 13)(The label of first or second conductivity type is arbitrary, and Salcedo refers to the N-type epitaxial layer as having the second type). Salcedo discloses a similar ESD protection device to Yang. Salcedo teaches the use of an epitaxial layer on the substrate into which to diffuse the components of the ESD device. Epitaxial layers are known equivalents to deep wells for the purpose of preparing a substrate for additional diffusions, presenting a prima facie case of obviousness. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using an epitaxial layer on the substrate. PNG media_image4.png 249 537 media_image4.png Greyscale Response to Arguments Applicant's arguments filed 26 June 2026 have been fully considered but they are not persuasive. The applicant argues that Yang defines region 250 as an N-well, therefore it cannot be called a diffusion region, simply because Yang distinguishes the description of 251 from 250 by calling 251 a N+ diffusion region. The applicant even goes so far as to suggest it is “improper to arbitrarily twist the meaning of the term ‘well’ to mean ‘diffusion region’”. The examiner respectfully points out that “(a) well is a region in the silicon substrate that is doped with either n-type or p-type impurities to allow the construction of the opposite type of MOS transistor” (https://www.watelectronics.com/differences-between-n-well-and-p-well-cmos-processes/, accessed 31 July 2026). Although the instant application has claims that are structure-related rather than method-related, a well is a diffusion region by definition in a typical CMOS process, wherein ion implantation is used to introduce dopant species into a substrate, before the species is diffused, usually at high temperature for a relatively long time, to create a relatively deep region of opposite conductivity type with limited lateral extent compared with the region into which it is introduced. Such a region can be referred to as an N- or P- (or just N or P) diffusion region, but is also commonly referred to by the term “N-well” or “P-well”. A well is, therefore, a specific type of diffusion region. Yang notes that 251 is an N+ diffusion region, the plus indicating a higher dopant concentration in that location than a diffusion region that would be called a well, having at least a relatively high implant dose, and likely a smaller diffusion budget (area under a curve of anneal or drive temperature vs. time). These are common industry terms and known technology, not arbitrary and not twisted. A well is a diffusion region by definition. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jul 30, 2023
Application Filed
Mar 31, 2026
Non-Final Rejection mailed — §103
May 12, 2026
Interview Requested
May 19, 2026
Examiner Interview Summary
May 19, 2026
Applicant Interview (Telephonic)
Jun 26, 2026
Response Filed
Aug 05, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12697688
SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD
3y 5m to grant Granted Aug 04, 2026
Patent 12666616
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+100.0%)
3y 6m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 6 resolved cases by this examiner. Grant probability derived from career allowance rate.

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