DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 12/12/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of USP 11,870,453 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to TD/Amendments
Applicant’s TD filed on 12/11/2025 has been reviewed and approved. However, the application cannot be placed in condition for allowance due to new ground rejections have been made as shown below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,8 10, 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Temes et al. (USP 5,369,403).
Regarding claim 1, Temes discloses a quantization DAC architecture in figure 3 that teaches: a first quantization stage (FIG. 3, #42) configured to receive a quantization error signal (FIG. 3, signal x and signal from 41) indicative of a quantization error of a source external to the first quantization stage, to sample the quantization error signal, to generate a first digital signal (signal coming from 42 and going to 44 and 41), to filter the first digital signal (FIG. 3, filter stage 41), and to generate a first noise-shaped digital output (signal going to 46); and a first digital filter (filter stage 56) configured to filter the first noise-shaped digital output and to generate a first stage digital output (output going to 60) (see figure 3 and its descriptions).
Regarding claim 8, Temes further teaches: wherein the first quantization stage is configured to receive an inversion (-EL) of the quantization error signal.
Regarding claim 10, Temes also discloses in figure 1 that a circuit comprising: a first quantization stage (16) configured to generate a quantization error signal (signal V, error eL); and a second quantization stage (22) configured to receive the quantization error signal (“The M-bit quantizer receives as its input the negative magnitude of error e.sub.L (contained in signal V in FIG. 1)”), to sample and quantize the quantization error signal (“The M-bit quantizer…generates a small M-bit digital quantization error e.sub.M in the process of quantizing e.sub.L to M significant bits.”), to generate a second digital signal (FIG. 1, signal W; “The loop 22 produces a digital signal w which includes the M significant bits and the error e.sub.M therein.”), to filter the second digital signal (FIG. 1, filter stage 24; “The filter stage 24 is a high-pass filter that reduces the part of the error e.sub.M which appears in the baseband, and passes the resultant filtered signal to the D/A converter 26”), and to generate a second noise-shaped digital output (output from 24 towards 26; “noise-shaped” from noise shaping loops 16 and 22; note that Temes additionally discloses that the final y2 signal is noise-shaped “The analog signal y.sub.2 at the output of the stage 28 is thus ideally the analog form of a negative noise-shaped e.sub.L.” and that the signal prior to 26 is digital as 26 is a digital-to-analog converter) (see figure 1 and its descriptions.
Regarding claim 14, Temes further teaches: wherein the second quantization stage is configured to receive an inversion (-EL) of the quantization error signal (see ele. 46 of fig. 3 and its descriptions).
Regarding claim 15, Temes discloses a quantization DAC architecture in figure 1 that teaches: filtering a first noise-shaped digital output (by noise shaping loop L bit quantizer, 16) with an equivalent signal transfer function to generate a first stage digital output (y1); filtering a second noise-shaped digital output (by noise shaping loop with M-bit quantizer, 22) with a first noise-shaping transfer function to generate a second stage digital output (y2); and combining (plus sign +) the first stage digital output (y1) and the second stage digital output (y2) to generate a digital analog-to-digital conversion (ADC) output signal having reduced quantization error based on said filtering the first noise-shaped digital output with the equivalent signal transfer function (see figure 1 and its descriptions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Temes et al. as applied to claim 1 above, and further in view of Kropfitsch et al. (US 2015/0180500).
Regarding claim 2, Temes fails to teach or suggest the first quantization stage includes an open loop voltage controlled oscillator (VCO)-based quantizer.
While, Kropfitsch et al.. discloses quantizer architecture in figure 3 that teaches using VCO quantizer is capable to produce output nonlinearities that can effect performance and accuracy of the DAC (see para. 0002).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to implement Kropfitsch’s VCO quantizer technique into Temes’s disclosures to improve output nonlinearities that can affect the performance and accuracy of the DAC.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Temes et al. as applied to claim 10 above, and further in view of Kropfitsch et al. (US 2015/0180500).
Regarding claim 12, Temes fails to teach or suggest the second quantization stage includes an open loop voltage controlled oscillator (VCO) quantizer.
While, Kropfitsch et al.. discloses quantizer architecture in figure 3 that teaches using VCO quantizer is capable to produce output nonlinearities that can effect performance and accuracy of the DAC (see para. 0002).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to implement Kropfitsch’s VCO quantizer technique into Temes’s disclosures to improve output nonlinearities that can affect the performance and accuracy of the DAC.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Temes et al. as applied to claim 10 above, and further in view of Huang et al (US 2019/0181880).
Regarding claim 13, Temes fails to teach or suggest the first quantization stage includes a successive approximation register (SAR) quantizer.
While, Huang et al. discloses SAR quantizer architecture in figure 1 that teaches SAR quantizer is capable of generating M highly-significant bits as a digital output signal and generating L lowly-significant bit(s) for the execution of noise shaping operation to reduce the demand for the circuit area of a DAC and lower the delay of critical path, so as to improve the performance and cut the cost of the invention (see para. 0007).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to implement SAR quantizer technique into Temes’s disclosures to reduce the demand for the circuit area of a DAC and lower the delay of critical path, so as to improve the performance and cut the cost of the invention.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: a second quantization stage configured to receive an analog input signal, to sample the analog input signal, to generate a second digital signal, to filter the second digital signal with a second noise shaping transfer function, to generate a second noise-shaped digital output, and to generate the quantization error signal based on a comparison of the analog input signal and the second noise-shaped digital output, wherein the second quantization stage includes a successive approximation register (SAR) quantizer.
Claim 4 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the quantization error signal is determined based on a residue voltage produced by the SAR quantizer during generation of the second noise-shaped digital output.
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the second quantization stage is configured to filter the second digital signal using a loop filter with the second noise-shaping transfer function.
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: a second digital filter configured to filter the second noise-shaped digital output with an equivalent signal transfer function and to generate a second stage digital output; anda combination circuit configured to combine the first stage digital output and the second stage digital output and to generate a digital analog-to-digital conversion (ADC) output signal with a second-order noise-shaping characteristic, wherein the combination circuit is an adder circuit.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the second quantization stage is further configured to delay the quantization error signal by a clock cycle, to generate a delayed quantization error signal, and to subtract the delayed quantization error signal from the analog input signal in a feedback loop.
Claim 9 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the first quantization stage is configured to filter the first digital signal with a first noise-shaping transfer function that approximates a first-order difference operation.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein: the first quantization stage is further configured to receive an analog input signal, to sample the analog input signal based on a first input clock signal, to generate a first digital signal, to filter the first digital signal with a first noise-shaping transfer function, to generate a first noise-shaped digital output, and to generate the quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output; and the second quantization stage is configured to sample the quantization error signal based on a second input clock signal that has a higher frequency than the first input clock signal and to filter the second digital signal with a second noise-shaping transfer function, the circuit further comprising :a digital up-sampler configured to increase a sampling rate of the first noise-shaped digital output by an amount proportional to a ratio of the second input clock signal and the first input clock signal and to generate an up-sampled digital output; a first digital filter configured to filter the up-sampled digital output with an equivalent signal transfer function and to generate a first stage digital output; a second digital filter configured to filter the second noise-shaped digital output with the first noise-shaping transfer function and to generate a second stage digital output with a second- order noise-shaping characteristic; and a combination circuit configured to combine the first stage digital output and the second stage digital output and to generate a digital analog-to-digital conversion (ADC) output signal with the second-order noise-shaping characteristic.
Claim 16 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: receiving an analog input signal at a first quantization stage; sampling the analog input signal at the first quantization stage to generate a first digital signal; filtering the first digital signal with the first noise-shaping transfer function to generate the first noise-shaped digital output; generating a quantization error signal at the first quantization stage based on a comparison of the analog input signal and the first noise-shaped digital output; receiving the quantization error signal at a second quantization stage; sampling the quantization error signal to generate a second digital signal; and filtering the second digital signal with a second noise-shaping transfer function to generate the second noise-shaped digital output, wherein the second stage digital output and the digital ADC output signal are generated with a second-order noise-shaping characteristic and the first quantization stage includes a successive approximation register (SAR) quantizer.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: determining the quantization error signal based on a residue voltage produced by the SAR quantizer during generation of the first noise-shaped digital output.
Claim 18 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the second quantization stage is configured to receive an inversion of the quantization error signal.
Claim 19 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the second noise-shaping transfer function approximates a first-order difference operation.
Claim 20 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: delaying the quantization error signal by a clock cycle to generate a delayed quantization error signal; and subtracting the delayed quantization error signal from the analog input signal in a feedback loop.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845