Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 07/27/2027. Currently, claims 1-14 and 18-30 are pending in the application. Claims 9, 11-14 and 18-27 have been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIU et al (CN 112331720 A). A machine English translation of LIU is provided with this office action.
Regarding claim 1, Figure 5 of LIU discloses a semiconductor device comprising:
a semiconductor substrate (100, page 2 of English translation of LIU);
a drain electrical contact (150) on the semiconductor substrate;
a source electrical contact (160) on the semiconductor substrate;
a barrier layer (140) over a channel region (130) of the semiconductor substrate between the drain electrical contact and the source electrical contact;
a gate layer (170) over the barrier layer, the gate layer including a first semiconductor portion (in contact with 231) and a second semiconductor portion (in contact with 232); and
a gate electrical contact (231+232, page 5 of English translate of LIU) contacting the gate layer, the gate electrical contact including a first metal portion (231) and a second metal portion (232), the first metal portion including a first metal layer contacting the gate layer and forming a first junction with the first semiconductor portion, the second metal portion (232) including a second metal layer over the first metal layer and extending through an opening in the first metal layer to contact the second semiconductor portion of the gate layer thereby forming a second junction with the second semiconductor portion, the first junction (schottky junction with 231) having a higher energy barrier height than the second junction (ohmic junction with 232).
Regarding claim 2, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 1, wherein the first junction has a first energy barrier height, the second junction has a second energy barrier height, the first energy barrier height is at least 1.7 electron volt (eV), and the second energy barrier height is less than 1.7 eV (some of the material meets these limitation).
Regarding claim 3, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 1, wherein: the first junction (with 231) is a Schottky junction; and the second junction (with 232) is an ohmic junction.
Regarding claim 4, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 1, wherein: the first junction (with 231) is a first Schottky junction; and the second junction is a second Schottky junction (considering 231 on both side of 232 and at an interface of 231 and 232 there would be a week schottky junction).
Regarding claim 5, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 1, wherein the first metal portion includes a metal material different from a metal material of the second metal portion (list of the material in page 3 of English translation teaches that the schottky and ohmic metals are different).
Regarding claim 6, Figure 5 of LIU discloses that the semiconductor device of claim 5, wherein the first metal portion and the second metal portion include at least one of: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAIN) (page 3 of English translation of LIU).
Regarding claim 8, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 5, wherein: the first metal portion (231) is over a first surface of the gate layer (170) parallel with a surface of the barrier layer (140), the first metal portion being over the first semiconductor portion at the first surface; and the second metal portion (232) is over the first surface, the second metal portion contacting the second semiconductor portion at the first surface (at 231).
Regarding claim 10, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 8, wherein: the second metal portion (232) is over the first surface (at 231) proximate the source electrical contact (160); and the source electrical contact (160) is notched on a side proximate to the gate layer (170) and in a channel length direction corresponding to where the second metal portion (232) contacts the first surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 28-30 are rejected under 35 U.S.C. 103 as being obvious over LIU et al (CN 112331720 A). A machine English translation of LIU is provided with this office action.
Regarding claim 7, Figure 5 of LIU (page 3 of English translation) discloses that the semiconductor device of claim 1, wherein the first metal portion and the second metal portion includes a same metal material (Pd is common) but does not explicitly teach that the metal material including at least one of: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAIN).
However, the Examiner takes an official notice that metal materials as claimed above is very well known in pertinent prior arts.
Regarding claims 28-30, Figure 5 of LIU does not explicitly teach that the semiconductor device of claim 1, wherein a surface area of the first semiconductor portion and a surface area of the second semiconductor portion are selected to obtain a gate leakage below a threshold while obtaining at least one of a stabilized gate overdrive voltage or an increased drain current. Or
The semiconductor device of claim 1, wherein a surface area of the first semiconductor portion is at least ten times of a surface area of the second semiconductor portion. Or
The semiconductor device of claim 1, wherein the second junction forms an ohmic resistor configured to bias the gate layer at a voltage that tracks a voltage applied to the gate electrical contact under both direct current (DC) and switching conditions.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to have an improved device manufactured less area and cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims, filed on 07/27/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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