Prosecution Insights
Last updated: April 19, 2026
Application No. 18/361,997

SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER

Non-Final OA §102§103
Filed
Jul 31, 2023
Examiner
AHMAD, KHAJA
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
750 granted / 928 resolved
+12.8% vs TC avg
Strong +27% interview lift
Without
With
+26.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
964
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
58.3%
+18.3% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 928 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This office action is in response to the Applicant Election filled on 12/23/2025. Currently, claims 1-27 are pending in the application. Claims 9 and 11-27 have been withdrawn from consideration. Election/Restrictions Applicant's election without traverse of Group I and Species IC (Figure 3), claims 1-8 and 10, in the reply filed on 12/23/2025 is acknowledged, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH et al (US 20210336045 A1). Regarding claim 1, Figure 2 of OH discloses a semiconductor device comprising: a semiconductor substrate (110+120, [0074]-[0075]); a drain electrical contact (171, [0079]) on the semiconductor substrate; a source electrical contact (172, [0079] on the semiconductor substrate; a barrier layer (130, [0077]) over a channel region of the semiconductor substrate between the drain electrical contact and the source electrical contact; a gate layer (140, [0080]) over the barrier layer, the gate layer including a first semiconductor portion (bottom portion) and a second semiconductor portion (140a, [0084]); and a gate electrical contact (150+160, [0087]) contacting the gate layer, the gate electrical contact including a first metal portion (160) and a second metal portion (150), the first metal portion forming a first junction (schottky, [0087]) with the first semiconductor portion (bottom portion), the second metal portion forming a second junction (ohmic, [0085]) with the second semiconductor portion (140a), the first junction and the second junction having different energy barrier heights (schottky and ohmic contacts has different energy barrier heights due to type of contact with different work function of the metal layers, [0085] and [0088]). Regarding claim 3, Figure 2 of OH discloses that the semiconductor device of claim 1, wherein: the first junction (with 160) is a Schottky junction; and the second junction (with 150) is an ohmic junction ([0085]-[0088]). Regarding claim 4, Figure 2 of OH discloses that the semiconductor device of claim 1, wherein: the first junction (with 160) is a first Schottky junction; and the second junction (there is some schottky junction present at the corner of 150 with 160) is a second Schottky junction ([0085]-[0088]) (Further defining 160 with two different portions, top and bottom, in claim 1 can meet this limitation because the barrier height of schottky is different as can be seen in Figure 3B). Regarding claim 5, Figure 2 of OH discloses that the semiconductor device of claim 1, wherein the first metal portion includes a metal material different from a metal material of the second metal portion ([0085]-[0088], considering different material for 150 and 160). Regarding claim 6, Figure 2 of OH discloses that the semiconductor device of claim 5, wherein the first metal portion and the second metal portion include at least one of: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAlN) ([0085]-[0088]). Regarding claim 7, Figure 2 of OH discloses that the semiconductor device of claim 1, wherein the first metal portion and the second metal portion includes a same metal material, the metal material including at least one of: titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), or titanium aluminum nitride (TiAlN) ([0085]-[0088]). Regarding claim 8, Figure 2 of OH discloses that the semiconductor device of claim 5, wherein: the first metal portion (160, [0086]) is over a first surface of the gate layer (140) parallel with a surface of the barrier layer (130), the first metal portion being over the first semiconductor portion at the first surface; and the second metal portion (150) is over the first surface, the second metal portion contacting the second semiconductor portion (140a, [0081]) at the first surface. Regarding claim 10, Figure 2 of OH discloses that the semiconductor device of claim 8, wherein: the second metal portion (150, [0084]) is over the first surface proximate the source electrical contact (171); and the source electrical contact is notched on a side proximate to the gate layer (140) and in a channel length direction corresponding to where the second metal portion contacts the first surface. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being obvious over OH et al (US 20210336045 A1). Regarding claim 2, Figure 2 of OH does not teach that the semiconductor device of claim 1, wherein the first junction has a first energy barrier height, the second junction has a second energy barrier height, the first energy barrier height is at least 1.7 electron volt (eV), and the second energy barrier height is less than 1.7 eV. However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to have an efficient device with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233. Examiner Notes A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jul 31, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+26.9%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 928 resolved cases by this examiner. Grant probability derived from career allow rate.

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