Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
This is a response to Amendment/Req. Reconsideration-After Non-Final Rejection filed by Applicant on 05/07/2026.
Claims 1-10 and 17-26 are still pending.
Claims 1, 17 and 21 have been amended.
Response to Arguments
Claim Rejection Under 35 U.S.C. §103:
Applicant’s arguments, see pages 6-9, filed 05/07/2026, with respect to the rejection(s) of claims 1-10 and 17-16 being rejected under AIA 35 U.S.C. § 103 as unpatentable over U.S. Patent Publication No. 2023/0067209 (hereinafter, "Chen") in view of U.S. Patent Publication No. 2013/0147505 (hereinafter, "Wang"), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Miwa et al. US 2024/0128134 in combination with the previously cited prior arts of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 and 17-26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2023/0067209 (Previously Cited; Hereinafter Chen) in view of Wang et al. US 2013/0147505 (Previously Cited; Hereinafter Wang) in further view of Miwa et al. US 2024/0128134 (Newly Cited; Hereinafter Miwa).
Regarding claim 1, Chen teaches a semiconductor package (Figs. 4-7; semiconductor package; 400), comprising:
a device under test (DUT) die (Figs. 4-7; semiconductor dies; 410);
a test point (Figs. 4-7; testing points; TPP) associated with the DUT die (Figs. 4-7; semiconductor dies; 410), the test point electrically coupled to a trace (Figs. 4-7; metal traces; 226a) of the semiconductor package (Figs. 4-7; semiconductor package; 400) and associated with a first spacing characteristic (Figs. 4-7; [0036-0045]; testing points; TPP).
Chen does not specifically teach a testing paddle associated with the DUT die; and a land provided on a surface of the testing paddle, wherein the land is electrically coupled to the test point and associated with a second spacing characteristic that is larger than the first spacing characteristic.
However, Wang does teach a testing paddle (Figs. 3-5, 7-12; probing pad; 30) associated with the DUT die (Figs. 3-5, 7-12; probing die; 100, 120); and a land (Figs. 3-5, 7-12; top surface; 21) provided on a surface of the testing paddle (Figs. 3-5, 7-12; probing pad; 30), wherein the land (Figs. 3-5, 7-12; top surface; 21) is electrically coupled to the test point (Figs. 3-5, 7-12; probing units; 40) and associated with a second spacing characteristic (Figs. 3-5, 7-12; top surface; 21) that is larger than the first spacing characteristic (Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
It would have been obvious before the effective filing date of the claimed invention to modify the testing apparatus of Chen by implementing the teachings of Wang regarding a testing paddle associated with the DUT die; and a land provided on a surface of the testing paddle, wherein the land is electrically coupled to the test point and associated with a second spacing characteristic that is larger than the first spacing characteristic; for the purpose of “testing integrated circuit devices formed on a semiconductor wafer” (See Wang; [0001]).
The combination of Chen and Wang does not specifically teach a testing paddle provided on a top surface of the DUT die.
However, Miwa does teach a testing paddle (Figs. 3-4; test pads, 108b) provided on a top surface of the DUT die (Figs. 3-4; semiconductor dies, 106).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Chen and Wang by implementing the teachings of Miwa regarding a testing paddle provided on a top surface of the DUT die; so that “wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process” (See Miwa; Abstract).
Regarding claim 2, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Chen further teaches wherein the first spacing characteristic is a first pitch between the test point and another test point associated with the DUT die (Chen; Figs. 4-7; [0036-0045]; testing points; TPP) and the second spacing characteristic is a second pitch between the land and another land provided on the surface of the testing paddle (Wang; Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
Regarding claim 3, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Wang further teaches wherein the second spacing characteristic is based, at least in part, on one or more dimensions of the land (Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
Regarding claim 4, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Chen further teaches wherein the DUT die is a first DUT die (Figs. 4-7; semiconductor dies; 410) and wherein the semiconductor package (Figs. 4-7; semiconductor package; 400) further comprises a second DUT die (Figs. 4-7; semiconductor dies; 410), wherein the testing paddle is provided between the first DUT die (Figs. 4-7; semiconductor dies; 410) and the second DUT die (Figs. 4-7; semiconductor dies; 410).
Regarding claim 5, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 4, wherein Chen further teaches wherein the test point associated with the first DUT die is a first test point (Figs. 4-7; testing points; TPP) and wherein the land provided on the surface of the testing paddle is electrically coupled to a second test point associated with the second DUT die (Figs. 4-7; testing points; TPP).
Regarding claim 6, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Wang further teaches wherein the test point (Figs. 3-5, 7-12; probing units; 40) is a die bond pad ([0025]; conductive bond pads).
Regarding claim 7, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Wang further teaches wherein a material of the testing paddle is selected from a group, comprising a printed circuit board (PCB) and a substrate (Figs. 3-5, 7-12; [0018]; probing pad; 30, PCB).
Regarding claim 8, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Chen further teaches further comprising a passive electronic component electrically coupled to the testing paddle ([0032-0035, 0043-0043; resistors, resistance).
Regarding claim 9, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 8, wherein Chen further teaches wherein the passive electronic component is a termination resistor ([0032-0035, 0043-0043; resistors, resistance).
Regarding claim 10, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 1, wherein Wang further teaches wherein the land is electrically coupled to the test point using a bond wire (Figs. 3-5, 7-12; top surface; 21; [0025]; conductive bond pads).
Regarding claim 17, Chen teaches a semiconductor package that may be used for device characterization (Figs. 4-7; semiconductor package; 400), the semiconductor package comprising:
a device under test (DUT) die (Figs. 4-7; semiconductor dies; 410);
a testing means (Figs. 4-7; testing points; TPP) associated with the DUT die (Figs. 4-7; semiconductor dies; 410), the testing means electrically coupled to a communication means of the semiconductor package (Figs. 4-7; semiconductor package; 400) and associated with a first spacing characteristic (Figs. 4-7; testing points; TPP).
Chen does not specifically teach a testing surface means coupled to the DUT die, the testing surface means comprising a connection means electrically coupled to the testing means, the connection means having a second spacing characteristic that is greater than the first spacing characteristic.
However, Wang does teach a testing surface means (Figs. 3-5, 7-12; probing pad; 30) coupled to the DUT die (Figs. 3-5, 7-12; probing die; 100, 120), the testing surface means (Figs. 3-5, 7-12; probing pad; 30) comprising a connection means (Figs. 3-5, 7-12; top surface; 21) electrically coupled to the testing means (Figs. 3-5, 7-12; probing units; 40), the connection means (Figs. 3-5, 7-12; top surface; 21) having a second spacing characteristic that is greater than the first spacing characteristic (Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
It would have been obvious before the effective filing date of the claimed invention to modify the testing apparatus of Chen by implementing the teachings of Wang regarding a testing surface means coupled to the DUT die, the testing surface means comprising a connection means electrically coupled to the testing means, the connection means having a second spacing characteristic that is greater than the first spacing characteristic; for the purpose of “testing integrated circuit devices formed on a semiconductor wafer” (See Wang; [0001]).
The combination of Chen and Wang does not specifically teach a testing surface means provided on the DUT die.
However, Miwa does teach a testing surface means (Figs. 3-4; test pads, 108b) provided on the DUT die (Figs. 3-4; semiconductor dies, 106).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Chen and Wang by implementing the teachings of Miwa regarding a testing surface means provided on the DUT die; so that “wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process” (See Miwa; Abstract).
Regarding claim 18, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 17, wherein Chen further teaches wherein the first spacing characteristic is a first pitch between the testing means and another testing means associated with the DUT die (Chen; Figs. 4-7; [0036-0045]; testing points; TPP) and the second spacing characteristic is a second pitch between the connection means and another connection means of the testing surface means (Wang; Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
Regarding claim 19, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 17, wherein Wang further teaches wherein the second spacing characteristic is based, at least in part, on one or more dimensions of the connection means (Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
Regarding claim 20, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 17, wherein Wang further teaches wherein a material of the testing surface means is selected from a group, comprising a printed circuit board (PCB) and a substrate (Figs. 3-5, 7-12; [0018]; probing pad; 30, PCB).
Regarding claim 21, Chen teaches a semiconductor package (Figs. 4-7; semiconductor package; 400), comprising:
a device under test (DUT) die (Figs. 4-7; semiconductor dies; 410);
a test point (Figs. 4-7; testing points; TPP) provided on a surface of the DUT die (Figs. 4-7; semiconductor dies; 410).
Chen does not specifically teach a testing paddle associated with the DUT die; and a land provided on a surface of the testing paddle and electrically coupled to the test point.
However, Wang does teach a testing paddle (Figs. 3-5, 7-12; probing pad; 30) associated with the DUT die (Figs. 3-5, 7-12; probing die; 100, 120); and a land (Figs. 3-5, 7-12; top surface; 21) provided on a surface of the testing paddle (Figs. 3-5, 7-12; probing pad; 30) and electrically coupled to the test point (Figs. 3-5, 7-12; probing units; 40).
It would have been obvious before the effective filing date of the claimed invention to modify the testing apparatus of Chen by implementing the teachings of Wang regarding a testing paddle associated with the DUT die; and a land provided on a surface of the testing paddle and electrically coupled to the test point; for the purpose of “testing integrated circuit devices formed on a semiconductor wafer” (See Wang; [0001]).
The combination of Chen and Wang does not specifically teach a testing paddle provided on a top surface of the DUT die.
However, Miwa does teach a testing paddle (Figs. 3-4; test pads, 108b) provided on a top surface of the DUT die (Figs. 3-4; semiconductor dies, 106).
It would have been obvious before the effective filing date of the claimed invention to modify the combination of Chen and Wang by implementing the teachings of Miwa regarding a testing paddle provided on a top surface of the DUT die; so that “wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process” (See Miwa; Abstract).
Regarding claim 22, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 21, wherein Chen further teaches wherein the test point (Figs. 4-7; testing points; TPP) is electrically coupled to a trace (Figs. 4-7; metal traces; 226a) of the semiconductor package (Figs. 4-7; semiconductor package; 400).
Regarding claim 23, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 21, wherein Wang further teaches wherein the land has a first set of dimensions and the test point has a second set of dimensions that are different from the first set of dimensions (Figs. 3-5, 7-12; top surface, probing pad; 21, 30).
Regarding claim 24, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 21, wherein Chen further teaches wherein the DUT die is a first DUT die (Figs. 4-7; semiconductor dies; 410) and wherein the semiconductor package further comprises a second DUT die (Figs. 4-7; semiconductor dies; 410), wherein the testing paddle is provided between the first DUT die and the second DUT die (Figs. 4-7; semiconductor dies; 410).
Regarding claim 25, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 21, wherein Wang further teaches wherein the test point (Figs. 3-5, 7-12; probing units; 40) is a bond pad ([0025]; conductive bond pads).
Regarding claim 26, the combination of Chen, Wang and Miwa teaches the semiconductor package of claim 21, wherein Wang further teaches wherein the land is electrically coupled to the test point using a bond wire (Figs. 3-5, 7-12; top surface; 21; [0025]; conductive bond pads).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ziglioli US 2017/0323834 - One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads.
Kim et al. US 2018/0299490 - A probe includes a beam and at least two tips. The beam transmits test signals to a device under test (DUT). The at least two tips are arranged on a first end portion of the beam in a direction at a predetermined angle to a length direction of the beam and contacts adjacent terminals of the DUT. The beam has a larger width that exceeds a sum of widths of the at least two tips in a width direction of the beam such that the probe has an improved current carrying capacity and is prevented from being damaged due to overcurrent.
Hussain US 2002/0004339 - A system level test socket for testing semiconductor packages having non-pin grid array footprints. The test socket having solder pads positioned on the test socket to form electrical connections with corresponding leads on the bottom of the semiconductor package. The test socket has internal connections connecting each solder pad with a corresponding connection on the bottom of the test socket. The test socket is mounted on a burn-in board, thus allowing a semiconductor package having a non-pin grid array footprint to be tested without requiring an interposer for converting the non-pin grid array footprint of the semiconductor package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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