Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oyamatsu, U.S. Patent 5,923,969.
Oyamatsu shows the invention as claimed including a semiconductor device comprising:
N-wells and P-wells (2 and 3) extending in a first direction (into the page) and alternately arranged in a second direction (in a left and right direction) orthogonal to the first direction; and
A dummy gate 38 formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, wherein: the dummy gate is formed in a region other than an end portion (for example, at an interface between doped regions 2 and 3) in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction (note that when giving the claims their broadest reasonable interpretation since the predetermined threshold is not defined, a well of any width reads on the claim) (for description of entire process, see col. 10-line 60 to col. 11-line 25 and figs. 13a-13b).
Concerning claim 2, note that the transistors are formed in the N-wells and P-wells (see figs. 13a-13b). Regarding forming these transistors using oblique halo ion implantation, note that this is a process limitation which is not given patentable weight since the claims are drawn to the product.
With respect to dependent claim 3, note that when giving the claim its broadest reasonable interpretation the well that has the width smaller than the predetermined threshold in the second direction is a well arranged at an end portion in the second direction of the N-wells and the P-wells that are alternately arranged in the second direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oyamatsu, U.S. Patent 5,923,969 in view of Champeix et al., US 2018/0097058.
Oyamatsu is applied as above but does not expressly disclose a well surrounding the N-wells and P-wells that are alternately arranged in the second direction. Champeix et al. discloses forming double and triple well configurations in order to protect against attacks (see paragraph 0024). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Oyamatsu so as to form a well surrounding the N-wells and P-wells in, for example, a double well configuration in order to protect against attacks on the circuit.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oyamatsu, U.S. Patent 5,923,969 in view of Shum, U.S. Patent 7,081,381.
Oyamatsu is applied as above but does not expressly disclose wherein a gate insulating film of a transistor formed in a well surrounding the N-wells and the P-wells is thicker than each of gate insulating films of transistors formed in the N-wells and the P-wells. Shum discloses forming a gate insulating film in a well surrounding other wells to be thicker than the gate insulating film of transistors formed in the wells that are surrounded (see, for example, fig. 8 and col. 2-line 33 to col. 3-line 31). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Oyamatsu so as to comprise the gate insulating film configurations as disclosed by Shum because such a configuration is shown by Shum to be suitable based upon the particular application of the individual devices.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oyamatsu, U.S. Patent 5,923,969.
Oyamatsu is applied as above but does not expressly disclose where the transistors form a logic circuit. However, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilizie the transistors of Oyamatsu in a logic circuit as this is a commonly used configuration in semiconductor device manufacturing. With respect to the transistors applying oblique ion implantation, note that these claims are directed to the product rather than the process and the particular process limitation does not have patentable significance unless it materially affects the product.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oyamatsu, U.S. Patent 5,923,969 as applied to claim 6 above, and further in view of Harashima et al., US 2009/0236672.
Oymatsu is applied as above but does not expressly disclose wherein the logic circuit forms a peripheral circuit, the peripheral circuit being configured to drive memory cells of a NAND nonvolatile memory. Harashima et al. discloses the use of a logic crcuit as a peripheral circuit that is configured to drive memory cells of a NAND nonvolatile memory (see paragraph 0033). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Oyamastu so as to comprise the claimed logic circuit configuration because Harashima et al. shows this to be a suitable use and common configuration for transistors in semiconductor devices.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly US 5,923,969, either singly or in combination, fails to anticipate or render obvious, the following limitations in combination with the other claimed limitations: the dummy gate is not arranged above the element isolation region at the end portion in the first direction of the well that has the width smaller than the predetermined threshold in the second direction, as required by dependent claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nakata et al., US 2004/0099924 discloses the formation of dummy gates 17 formed on isolation regions (see, for example, figs. 6B and 7B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
April 9, 2026
Prosecution Insights