DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on March 9th, 2026, has been entered.
Upon entrance of the Amendment, claim 1 was amended. Claims 1-20 are currently pending.
Claim 1 was objected to because of informalities. Claim 1 has been amended as suggested. The objection of claim 1 has been overcome and is withdrawn.
Response to Arguments
Applicant's arguments filed on March 9th, 2026 have been fully considered but they are not persuasive.
The Applicant has argued “Jin teaches electrolytic tin plating - NOT immersion tin plating … electrolytic tin plating and immersion tin plating are substantially different.” The examiner agrees that Jin discloses electrolytic tin plating. However, the claim does not require immersion tin plating process is used. The claim recites “immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating.” Actually, the process step of “immersing the singulated IC packages in a bath of immersion tin” is involved in the electrolytic tin plating process, and as a result, tin plating is formed. Thus, the electrolytic tin plating of Jin is concluded to meet the limitations of the claim.
The Applicant has argued “one having ordinary skill in the art would NOT have been motivated to combine Lee, which teaches a single non-tin electro-plating process to protect the leads & die attach pad. There is need for any subsequent "bath of immersion tin" to be deposited on any surface of the leads or die attach pad. Fan, on the other hand, requires two different steps of plating an initial plating step that is electroplating using the top of the leadframe strip with "silver (Ag) or nickel and palladium (Ni/Pd) or nickel and gold (Ni/Au) (FIG. ID)" and the bottom side of the leadframe strip with "Ag or Ni/Pd or Ni/Au"…” The argument is not persuasive, because not all teachings of Fan were incorporated into Lee. The only deficiency of Lee is “immersing packages in a bath of immersion tin to form immersion tin plating”, and this deficiency is cured by Fan.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-7, and 12-14 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jin et al. (U.S. Patent No. 11,876,003).
Regarding to claim 1, Jin teaches a method for forming integrated circuit (IC) packages, the method comprising:
mounting a tape on a mold compound of a strip of flat no-leads IC packages (Fig. 4, column 8, lines 12-14);
sawing the mold compound of the strip of flat no-leads IC packages to form singulated IC packages mounted on the tape (Fig. 5B, column 10, lines 12-15); and
immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating on a flank of leads of the singulated IC packages (Fig. 7, column 11, lines 23-36).
Regarding to claim 6, Jin teaches the singulated IC packages of the strip of flat noleads IC packages have copper interconnects (column 1, lines 29; column 5, lines 36-38).
Regarding to claim 7, Jin teaches
etching exposed copper of the copper interconnects (column 5, lines 40-41); and
dipping the singulated IC packages in the bath of immersion tin such that the etched exposed copper is submerged in the immersion tin (column 7, lines 50-56).
Regarding to claim 12, Jin teaches encapsulating the strip of flat no-leads IC packages in the mold compound, wherein a bottom and the flank of the leads are exposed (Fig. 7).
Regarding to claim 13, Jin teaches applying matted tin plating to the bottom of leads of the strip of flat no-leads IC packages prior to the dipping (column 7, lines 39-43).
Regarding to claim 14, Jin teaches the immersion tin of the bath of immersion tin is non-reactive to the matted tin plating (column 7, lines 40-44).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent No. 6,773,961) in view of Fan et al. (U.S. Patent No. 7,049,177).
Regarding to claim 1, Lee teaches a method for forming integrated circuit (IC) packages, the method comprising:
Mounting a tape on a mold compound of a strip of flat no-leads IC packages (Fig. 6, mounting tape 200 on mold compound of a strip of flat no-leads IC packages);
sawing the mold compound of the strip of flat no-leads IC packages to form singulated IC packages mounted on the tape (Fig. 7); and
plating the singulated IC packages to form tin plating on a flank of leads of the singulated IC packages (column 4, lines 51-54).
Lee does not specially disclose the plating is performed by immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating.
Fan discloses a plating is performed by immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating (Figs. 1J-K, column 5, lines 3-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee in view of Fan to have the tin plating performed by immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating, in order to improve solderability for the pads and contact areas.
Regarding to claim 2, Lee as modified is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 2 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 3, Lee as modified is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 3 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 4, Lee as modified is silent as to the height of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating has a height of at least 50 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 5, Lee as modified is silent as to solution in the bath of immersion tin. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to form the bath of immersion tin with a solution of tin, tin salt and an activator since plating solution was known in the art.
Regarding to claim 6, Lee teaches the singulated IC packages of the strip of flat no-leads IC packages have copper interconnects (column 3, lines 60-62).
Regarding to claim 7, Fan discloses etching exposed copper of the copper interconnects (column 4, lines 49-53) and dipping the singulated IC packages in the bath of immersion tin such that the etched exposed copper is submerged in the immersion tin (column 5, lines 1-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Lee in view of Fan to etch exposed copper of the copper interconnects and dip the singulated IC packages in the bath of immersion tin such that the etched exposed copper is submerged in the immersion tin, in order to increase contact area, thus to reduce contact resistance.
Regarding to claim 12, Lee teaches encapsulating the strip of flat no-leads IC packages in the mold compound, wherein a bottom and the flank of the leads are exposed (Fig. 8).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent No. 6,773,961) and Fan et al. (U.S. Patent No. 7,049,177), as applied to claims 1 and 6-7 above, in view of Ehrsam et al. (U.S. Patent No. 5,466,360).
Regarding to claim 8, Lee as modified is silent as to rinsing step. Ehrsam discloses rinsing the singulated IC packages before and after dipping (Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee in view of Ehrsam to rinse the singulated IC packages before and after the dipping in order to remove contaminations, thus to increase reliability. Further, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to rinse the singulated IC packages before and after the dipping since it was known in the art that rinsings are need to clean workpieces before and after treatments with chemicals.
Regarding to claim 9, Lee as modified is silent as to rinsing step. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to rinse the singulated IC packages before and after the etching since it was known in the art that rinsings are need to clean workpieces before and after treatments with chemicals.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent No. 6,773,961) and Fan et al. (U.S. Patent No. 7,049,177), as applied to claims 1 and 6-7 above, in view of Sbuelz (U.S. Patent No. 4,268,957).
Regarding to claim 10, Lee as modified does not disclose the immersing further comprises shocking the bath of tin in response to the dipping. Sbuelz discloses an immersing comprises shocking the bath of tin in response to the dipping (Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee in view of Sbuelz to shock the bath of tin in response to the dipping, in order to increase plating thickness uniformity.
Regarding to claim 11, Lee as modified discloses immersing further comprises vibrating the bath of tin during the dipping (Sbuelz, Fig. 2).
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (U.S. Patent No. 11,876,003), as applied to claim 1 above.
Regarding to claim 2, Jin is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 2 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 3, Jin is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 3 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 4, Jin is silent as to the height of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating has a height of at least 50 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 5, Jin is silent as to solution in the bath of immersion tin. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to form the bath of immersion tin with a solution of tin, tin salt and an activator since plating solution was known in the art.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (U.S. Patent No. 11,876,003), as applied to claims 1 and 6-7 above, in view of Ehrsam et al. (U.S. Patent No. 5,466,360).
Regarding to claim 8, Jin is silent as to rinsing step. Ehrsam discloses rinsing the singulated IC packages before and after dipping (Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin in view of Ehrsam to rinse the singulated IC packages before and after the dipping in order to remove contaminations, thus to increase reliability.
Regarding to claim 9, Jin is silent as to rinsing step. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to rinse the singulated IC packages before and after the etching since it was known in the art that rinsings are need to clean workpieces before and after treatments with chemicals.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (U.S. Patent No. 11,876,003), as applied to claims 1 and 6-7 above, in view of Sbuelz (U.S. Patent No. 4,268,957).
Regarding to claim 10, Jin does not disclose the immersing further comprises shocking the bath of tin in response to the dipping. Sbuelz discloses an immersing comprises shocking the bath of tin in response to the dipping (Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jin in view of Sbuelz to shock the bath of tin in response to the dipping, in order to increase plating thickness uniformity.
Regarding to claim 11, Jin as modified discloses immersing further comprises vibrating the bath of tin during the dipping (Sbuelz, Fig. 2).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (U.S. Patent No. 11,876,003).
Regarding to claim 15, Jin teaches an integrated circuit (IC) package comprising:
a die mounted on a flat no-leads interconnect (Figs. 11-12); and
a mold compound encapsulating the die on a top side of the flat no-leads interconnect, wherein a flank of leads of the flat no-leads interconnect have an immersion tin plating (Figs. 11-12, column 11, lines 23-36; column 14, lines 18-22).
Jin is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 2 micrometers in order to obtain sufficient solderability of conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 16, Jin teaches t the leads of the flat no-leads interconnect are formed with copper (column 1, lines 29; column 5, lines 36-38).
Regarding to claim 17, Jin is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating having a thickness greater than 3 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 18, Jin is silent as to the thickness of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating has a thickness sufficient to prevent consumption by the copper leads of the flat no-leads interconnect for at least 1 year in order to make the device useful and marketable, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 19, Jin teaches a bottom side of the leads of the IC package has matted tin plating (column 7, lines 39-43).
Regarding to claim 20, Jin is silent as to the height of the plating. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the immersion tin plating has a height of at least 50 micrometers in order to obtain sufficient solderability and conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897
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