DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant's arguments filed 1/16/2026 have been fully considered but they are not persuasive. Applicant argues the prior art does not teach the limitations of claims 1, 16 and 20, i.e. “the source select lines/select line structure includes an epitaxial pattern.”
Regarding claims 1 and 16, in response to applicant's argument that “Lee 1 is silent regarding any epitaxial layer or pattern” (See Remarks, Pg 10, Paragraph 10), a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
6. Applicant’s arguments, see Specification, filed 1/16/2026, with respect to the objection of the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-3, 9-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, Nam Jae et al. (Pub No. US 20220077182 A1) (hereinafter, Lee 1).
Lee 1, Figs 3A/4A: Embodiments of semiconductor memory device
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Re Claim 1, (Original) Lee 1 teaches a semiconductor device comprising:
a gate structure (Gate stack; G1; Fig 4A; ¶[0033]) located between a bit line (Bit lines; BL; Fig 4A; ¶[0031]) and a source structure (Common source layer; CSL; Fig 4A; ¶[0025]), the gate structure including stacked word lines (Word lines; WL; Fig 3A; ¶[0028]);
a select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) located between the gate structure and the source structure, the select line structure including an epitaxial pattern (Silicon layer; 13'; Fig 4A; ¶[0075]) and a silicide layer (Metal silicide layer; 15'; Fig 4A; ¶[0075]); and
a channel structure (Channel pillars; CH'; Fig 4A; ¶[0035]) extending through the gate structure and the select line structure, the channel structure connected between (Per Fig 4A CH' connects CSL' to BL') the source structure and the bit line.
Lee 1, Fig 10A: Silicide lower over source select line epitaxial pattern
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Re Claim 2, (Original) Lee 1 teaches the semiconductor device of claim 1, wherein the silicide layer (Metal layer; 789; Fig 10A; ¶[0158]; Note: Fig 10A shows an embodiment of the silicide layer over the epitaxial pattern) surrounds an upper surface (Upper surface of 707A) and sidewalls (Sidewalls of 707A) of the epitaxial pattern (Preliminary select line/Silicon layer; 13A/707A; Figs 5/10A; ¶[0158]).
Re Claim 3, (Original) Lee 1 teaches the semiconductor device of claim 2, wherein the silicide layer (Metal layer; 789; Fig 10A; ¶[0158]; Note: Fig 10A shows an embodiment of the silicide layer over the epitaxial pattern) includes nickel silicide (Nickel; ¶[0159]).
Re Claim 9, (Original) Lee 1 teaches the semiconductor device of claim 1, wherein the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) includes source select lines (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) and the gate structure (Gate stack; G1; Fig 4A; ¶[0033]) includes drain select lines (Drain select lines; DSL1/DSL2/DSL3; fig 4A; ¶[0028]).
Re Claim 10, (Currently Amended) Lee 1 teaches the semiconductor device of claim 9, further comprising
an isolation structure (Source isolation insulating layer between SSL1'/SSL2'; SS1'; Fig 4A; ¶[0072]) located between the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) and the source structure (Common source layer; CSL; Fig 4A; ¶[0025]),
the isolation structure extending between (Left side SS1' extends between SSL1'/SSL2''; Fig 4A) the source select lines (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]).
Re Claim 11, (Currently Amended) Lee 1 teaches the semiconductor device of claim 9, further comprising
a first isolation structure (Drain isolation insulating layer; SD; Fig 4A; ¶[0037]) located in the gate structure (Gate stack; G1; Fig 4A; ¶[0033]) and extending between the drain select lines (Drain select lines; DSL1/DSL2/DSL3; fig 4A; ¶[0028]).
Re Claim 12, (Currently Amended) Lee 1 teaches the semiconductor device of claim 11, further comprising
a second isolation structure (Source isolation insulating layer between SSL2' and SSL3'; SS/SS1'; Fig 4A; ¶[0072]) located between the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) and the source structure (Common source layer; CSL; Fig 4A; ¶[0025]), extending between the source select lines (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]),
and located to face (Facing SD' from D1; Fig 4A) the first isolation structure (Drain isolation insulating layer; SD; Figs 3A/4A; ¶[0037]) with the word lines interposed therebetween (Word lines; WL; Fig 3A; ¶[0028]).
Re Claim 13, (Currently Amended) Lee 1 teaches the semiconductor device of claim 1, further comprising
a slit structure (Gate isolation insulating layer; SG; Fig 3A; ¶[0034]) extending into the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 3A; ¶[0028]) through the gate structure (Gate stack; G1; Fig 3A; ¶[0033]).
Re Claim 14, (Currently Amended) Lee 1 teaches the semiconductor device of claim 13, further comprising
an isolation structure (Source isolation insulating layer; SS2'; Fig 4A; ¶[0072]) located between the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) and the source structure (Common source layer; CSL; Fig 4A; ¶[0025]),
the isolation structure extending into the select line structure to be connected (Extends into region of SSL1'/SSL3' connecting to SG'; Fig 4A) to the slit structure (Gate isolation insulating layer; SG; Fig 4A; ¶[0034]) .
Re Claim 15, (Original) Lee 1 teaches the semiconductor device of claim 1, further comprising:
a peripheral circuit (Peripheral circuit structure; 50/50'; Figs 3A/4A; ¶[0085]);
a bonding structure (Bonding metal patterns; 125/175; Fig 3A; ¶¶[0059-0060]) bonding the peripheral circuit to a cell array (Region above 50; Fig 3A), wherein the cell array includes the gate structure (Gate stack; G1; Fig 4A; ¶[0033]), the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]), and the channel structure (Channel pillars; CH'; Fig 4A; ¶[0035]) .
Re Claim 16, (Currently Amended) Lee 1 teaches a semiconductor device comprising:
a cell array (Region above 50; Fig 3A) including a gate structure (Gate stack; G1; Fig 4A; ¶[0033]) including drain select lines (Drain select lines; DSL1/DSL2/DSL3; fig 4A; ¶[0028]) and word lines (Word lines; WL; Fig 3A; ¶[0028]) and source select lines (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) each including an epitaxial pattern (Silicon layer; 13'; Fig 4A; ¶[0075]) and a silicide layer (Metal silicide layer; 15'; Fig 4A; ¶[0075]); ;
a first bonding pad (First bonding metal pattern; 175; Fig 3A; ¶¶[0059-0060]) electrically connected (Through interconnects (not labelled) in 171; Fig 3A) to the cell array;
a peripheral circuit (Peripheral circuit structure; 50/50'; Figs 3A/4A; ¶[0085]); and
a second bonding pad (Second bonding metal patterns; 125; Fig 3A; ¶¶[0059-0060]) electrically connected to the peripheral circuit and the first bonding pad.
Re Claim 17, (Original) Lee 1 teaches the semiconductor device of claim 16, wherein the silicide layer (Metal layer; 789; Fig 10A; ¶[0158]; Note: Fig 10A shows an embodiment of the silicide layer over the epitaxial pattern) surrounds an upper surface (Upper surface of 707A) and sidewalls (Sidewalls of 707A) of the epitaxial pattern (Preliminary select line/Silicon layer; 13A/707A; Figs 5/10A; ¶[0158]), and wherein the silicide layer includes nickel silicide (Nickel; ¶[0159]).
Re Claim 20, (New) Lee 1 teaches a semiconductor device comprising:
a gate structure (Gate stack; G1; Fig 4A; ¶[0033]) including conductive layers (Word lines; WL; Fig 3A; ¶[0028]) alternately stacked with insulating layers (Interlayer insulating layer; 21; Fig 3A; ¶[0051]);
a select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) disposed over the gate structure,
the select line structure including a first silicide layer (Left-hand metal silicide layers; 15'; Fig 4A; ¶[0075]), a second silicide layer (Right-hand metal silicide layers; 15'; Fig 4A; ¶[0075]), and
an epitaxial pattern (Silicon layer; 13'; Fig 4A; ¶[0075]) between the first silicide layer and the second silicide layer; and
a channel structure (Channel pillars; CH'; Fig 4A; ¶[0035]) extending through the gate structure and the select line structure.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 4-6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Nam Jae et al. (Pub No. US 20220077182 A1) (hereinafter, Lee 1) as applied to claims 1 and 16 above, and further in view of Lee, Nam Jae et al. (Pub No. US 20210217769 A1) (hereinafter, Lee 2).
Lee 2, Figs 5A/5B: Embodiment of semiconductor device and silicide/epitaxial layers
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Re Claim 4, (Original) Lee 1 does not teach the semiconductor device of claim 1, wherein the silicide layer is located under the epitaxial pattern.
In the same field of endeavor, Lee 2 teaches the semiconductor device of claim 1, wherein the silicide layer (Third select gate layer; 189; Figs 5A/5B; ¶[0085]) is located under (189 is under 181; Fig 5B) the epitaxial pattern (First select gate layer; 181; Figs 5A/5B; ¶[0082]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a silicide layer located under the epitaxial pattern [of the select line structure], as taught by Lee 2 with the semiconductor device as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success because the silicide layer can serve as a diffusion barrier for preventing diffusion of metal from surrounding metal layers into the epitaxial pattern (Lee 2 (¶[0147]).
Re Claim 5, (Original) Lee 1 does not teach the semiconductor device of claim 4, wherein the silicide layer includes titanium silicide.
In the same field of endeavor, Lee 2 teaches the semiconductor device of claim 4, wherein the silicide layer (Third select gate layer; 189; Figs 5A/5B; ¶[0085]) includes titanium silicide (Titanium silicide material (TiSi); ¶[0085]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a silicide layer including titanium silicide, as taught by Lee 2, with the silicide layer under the epitaxial pattern within the semiconductor device as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success because titanium silicide is known for its Fermi level position interfacing the midgap of the surrounding [silicon] epitaxial pattern, thus reducing contact resistance, especially if silicon is a n-type or p-type doped.
Re Claim 6, (Original) Lee 1 teaches the semiconductor device of claim 1, wherein the select line structure (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) comprises:
a nickel silicide layer (Metal layer; 789; Fig 10A; ¶[0158]; Note: Fig 10A shows an embodiment of the silicide layer over the epitaxial pattern) located on the epitaxial pattern (Preliminary select line; 707A; Fig 10A; ¶[0158]).
However, Lee 1 does not teach a titanium silicide layer;
the epitaxial pattern located on the titanium silicide layer.
In the same field of endeavor, Lee 2 teaches a titanium silicide layer (Third select gate layer; 189; Figs 5A/5B; ¶[0085]);
the epitaxial pattern (First select gate layer; 181; Figs 5A/5B; ¶[0082]) located on (181 is on 189; Fig 5B) the titanium silicide layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a select line structure comprising a epitaxial pattern located on a titanium silicide layer, as taught by Lee 2, with the nickel silicde layer located on the epitaxial pattern as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success in order to obtain reduced contact resistance given the nickel silicide abutting the epitaxial pattern (Lee 1, ¶[0161]) and to have a diffusion barrier for metals given the titanium silicide layer (Lee 2, ¶[0147]).
Re Claim 18, (Original) Lee 1 does not teach the semiconductor device of claim 16, wherein the silicide layer is located under the epitaxial pattern, and wherein the silicide layer includes titanium silicide.
In the same field of endeavor, Lee 2 teaches the semiconductor device of claim 16, wherein the silicide layer (Third select gate layer; 189; Figs 5A/5B; ¶[0085]) is located under (189 is under 181; Fig 5B) the epitaxial pattern (First select gate layer; 181; Figs 5A/5B; ¶[0082]), and wherein the silicide layer includes titanium silicide (Titanium silicide material (TiSi); ¶[0085]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a silicide layer located under the epitaxial pattern [of the select line structure] wherein the silicide layer includes titanium silicide, as taught by Lee 2 with the semiconductor device as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success because the silicide layer can serve as a diffusion barrier for preventing diffusion of metal from surrounding metal layers into the epitaxial pattern (Lee 2 (¶[0147]). Further, titanium silicide is known for its Fermi level position interfacing the midgap of the surrounding [silicon] epitaxial pattern, thus reducing contact resistance, especially if silicon is a n-type or p-type doped.
11. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Nam Jae et al. (Pub No. US 20220077182 A1) (hereinafter, Lee 1) as applied to claim 1 above, and further in view of Liao, Ting-Feng et al. (Pub No. US 20230157016 A1) (hereinafter, Liao).
Liao, Fig 1: Memory device illustrating epitaxial patterns at base of channels
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Re Claim 7, (Original) Lee 1 teaches the semiconductor device of claim 1, wherein the epitaxial pattern (Preliminary select line/Silicon layer; 13A/707A; Figs 5/10A; ¶[0158]) includes an undoped first epitaxial pattern (Silicon layer; 13'/13A; Figs 4B/5; ¶[0082]).
In the same field of endeavor, Liao teaches wherein the epitaxial pattern (Second/Fourth polysilicon layer; 102/104; Fig 1; ¶[0015]) a doped second epitaxial pattern (Fourth polysilicon layer; 104; Fig 1; ¶[0015]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a doped epitaxial pattern, as taught by Liao, with an undoped epitaxial pattern as taught by Lee 1 to form a two-layer epitaxial pattern. One would have been motivated to do this with a reasonable expectation of success in order to keep conductivity of the epitaxial patterns optimal, such that an undoped and doped epitaxial pattern may be positioned to prevent carrier leakage from the vertical channels.
Re Claim 8, (Original) Lee 1 does not teach the semiconductor device of claim 7, wherein the doped second epitaxial pattern includes at least one of phosphorus (P) and boron (B).
In the same field of endeavor, Liao teaches the semiconductor device of claim 7, wherein the doped second epitaxial pattern (Fourth polysilicon layer; 104; Fig 1; ¶[0015]) includes at least one of phosphorus (P) and boron (B) (P-type dopants, i.e. Boron (B); ¶[0015]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a doped second epitaxial pattern including at least one of phosphorus (P) and boron (B), as taught by Liao, with the semiconductor device as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success in order to optimize leakage of carriers from the vertical channels corresponding to the n-type or p-type dopants used within the second epitaxial pattern.
12. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Nam Jae et al. (Pub No. US 20220077182 A1) (hereinafter, Lee 1) as applied to claim 16 above, and further in view of Hu, Yushi et al. (Pub No. US 20210005621 A1) (hereinafter, Hu).
Hu, Fig 1: Embodiment of memory device with conductive regions, e.g. select lines
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Re Claim 19, (Original) Lee 1 teaches the semiconductor device of claim 16, wherein each of the source select lines (Source select lines; SSL1/SSL2/SSL3; Fig 4A; ¶[0028]) comprises:
a nickel silicide layer (Metal layer; 789; Fig 10A; ¶[0158]; Note: Fig 10A shows an embodiment of the silicide layer over the epitaxial pattern).
However, Lee 1 does not teach a titanium silicide layer;
the epitaxial pattern located between the titanium silicide layer and the nickel silicide layer.
In the same field of endeavor, Hu teaches a titanium silicide layer (Titanium silicide, e.g. located on or near conduction region 158; Fig 1; ¶[0055]);
the epitaxial pattern (Source conductor layer/Conduction region; 144/158; Fig 1; ¶[0054]) located between the titanium silicide layer and the nickel silicide layer (Per ¶[0054] In some embodiments, conduction regions 158 and 160 each includes one or more metal silicides, such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, and tungsten silicide and per ¶[0055] source conductor layer 144 can be patterned to form any suitable layout with different numbers of conduction regions and isolation regions in different arrangements).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined an epitaxial pattern located between a titanium silicide layer and a nickel silicide layer, as taught by Hu, with the nickel silicide layer located on the epitaxial pattern as taught by Lee 1. One would have been motivated to do this with a reasonable expectation of success in order to obtain reduced contact resistance given the nickel silicide abutting the epitaxial pattern and to have a diffusion barrier for metals given the titanium silicide layer, such that the source conductor layer can provide an electrical connect between one or more NAND strings with lowered resistance (Hu, ¶[0053]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Kim, Kwang-Soo (Pub No. US 20170221813 A1) discloses an integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.
[2] Kanamori, Kohji et al. (Pub No. US 20210091093 A1) discloses a three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
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/T.E.D./
Examiner
Art Unit 2817
Supervisory Patent Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/
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